finish.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.37 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.01 / 0.38 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: Finish.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Finish.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Finish"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : Finish
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : Finish.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "Z:/work/speedmes/can2.vhd" in Library work.
Entity <cancommunication> compiled.
Entity <cancommunication> (Architecture <behavioral>) compiled.
Compiling vhdl file "Z:/work/speedmes/speed.vhd" in Library work.
Architecture behavioral of Entity speed is up to date.
Compiling vhdl file "Z:/work/speedmes/SignalFlash.vhd" in Library work.
Entity <SignalFlash> compiled.
Entity <SignalFlash> (Architecture <Behavioral>) compiled.
Compiling vhdl file "Z:/work/speedmes/Finish.vhf" in Library work.
Entity <finish> compiled.
Entity <finish> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <Finish> (Architecture <behavioral>).
Entity <Finish> analyzed. Unit <Finish> generated.

Analyzing Entity <cancommunication> (Architecture <behavioral>).
Entity <cancommunication> analyzed. Unit <cancommunication> generated.

Analyzing Entity <speed> (Architecture <behavioral>).
Entity <speed> analyzed. Unit <speed> generated.

Analyzing Entity <signalflash> (Architecture <behavioral>).
Entity <signalflash> analyzed. Unit <signalflash> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <signalflash>.
    Related source file is "Z:/work/speedmes/SignalFlash.vhd".
    Found 1-bit register for signal <flash16>.
    Found 1-bit register for signal <flash>.
    Found 5-bit comparator greater for signal <$n0003> created at line 50.
    Found 5-bit adder for signal <$n0005> created at line 44.
    Found 5-bit up counter for signal <scaler>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <signalflash> synthesized.


Synthesizing Unit <speed>.
    Related source file is "Z:/work/speedmes/speed.vhd".
WARNING:Xst:643 - The result of a 32x8-bit multiplication found at "Z:/work/speedmes/speed.vhd" line 96 is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 9-bit register for signal <s>.
    Found 32-bit adder for signal <$n0005>.
    Found 32-bit adder for signal <$n0010>.
    Found 8-bit adder for signal <$n0013> created at line 100.
    Found 34-bit adder for signal <$n0018> created at line 70.
    Found 35-bit adder for signal <$n0019> created at line 70.
    Found 36-bit adder for signal <$n0020> created at line 70.
    Found 37-bit adder for signal <$n0021> created at line 70.
    Found 38-bit adder for signal <$n0022> created at line 70.
    Found 39-bit adder for signal <$n0023> created at line 70.
    Found 40-bit adder for signal <$n0024> created at line 70.
    Found 1-bit 4-to-1 multiplexer for signal <$n0028>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0036>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0037>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0038>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0039>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0040>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0042>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0043>.
    Found 5-bit adder for signal <$n0044> created at line 64.
    Found 23-bit adder for signal <$n0045> created at line 61.
    Found 41-bit adder for signal <$n0046> created at line 70.
    Found 32-bit adder for signal <$n0047>.
    Found 32-bit adder for signal <$n0048>.
    Found 32-bit adder for signal <$n0049>.
    Found 32-bit adder for signal <$n0050>.
    Found 32x8-bit multiplier for signal <$n0053> created at line 96.
    Found 32-bit comparator greater for signal <$n0059> created at line 97.
    Found 32-bit comparator greatequal for signal <$n0065> created at line 69.
    Found 32-bit comparator greatequal for signal <$n0067> created at line 75.
    Found 32-bit comparator greatequal for signal <$n0069> created at line 81.
    Found 32-bit comparator less for signal <$n0074> created at line 88.
    Found 23-bit register for signal <clkcount>.
    Found 5-bit register for signal <count>.
    Found 1-bit register for signal <flag>.
    Found 32-bit up counter for signal <sensorcount>.
    Summary:
	inferred   1 Counter(s).
	inferred  38 D-type flip-flop(s).
	inferred  17 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   5 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <speed> synthesized.


Synthesizing Unit <cancommunication>.
    Related source file is "Z:/work/speedmes/can2.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 40                                             |
    | Inputs             | 6                                              |
    | Outputs            | 12                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0013 (positive)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000                                          |
    | Power Up State     | 00000                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <AD>.
    Found 1-bit register for signal <CS>.
    Found 1-bit register for signal <LED_A1>.
    Found 1-bit register for signal <RD>.
    Found 8-bit register for signal <STATUS>.
    Found 1-bit register for signal <WR>.
    Found 1-bit register for signal <ALE>.
    Found 16-bit comparator greatequal for signal <$n0013> created at line 76.
    Found 8-bit 4-to-1 multiplexer for signal <$n0031>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0036>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0039>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0041>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0044>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0046>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0048>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 16-bit adder for signal <$n0058> created at line 75.
    Found 6-bit subtractor for signal <$n0061> created at line 91.
    Found 5-bit adder for signal <$n0062>.