communication.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: communication.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "communication.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "communication"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : communication
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : communication.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "Z:/work/speedmes/communication.vhd" in Library work.
Entity <communication> compiled.
Entity <communication> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <communication> (Architecture <Behavioral>).
WARNING:Xst:828 - "Z:/work/speedmes/communication.vhd" line 31: Constant <half_period> of type Time is ignored.
WARNING:Xst:819 - "Z:/work/speedmes/communication.vhd" line 40: The following signals are missing in the process sensitivity list:
   cale, crd, cwr, AD.
INFO:Xst:1304 - Contents of register <AD> in unit <communication> never changes during circuit operation. The register is replaced by logic.
Entity <communication> analyzed. Unit <communication> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <data> in unit <communication> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <communication>.
    Related source file is "Z:/work/speedmes/communication.vhd".
WARNING:Xst:1306 - Output <CS> is never assigned.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:1306 - Output <ALE> is never assigned.
WARNING:Xst:653 - Signal <cale> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <data> is assigned but never used.
WARNING:Xst:737 - Found 1-bit latch for signal <crd>.
WARNING:Xst:737 - Found 1-bit latch for signal <RD>.
WARNING:Xst:737 - Found 1-bit latch for signal <cwr>.
WARNING:Xst:737 - Found 1-bit latch for signal <WR>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006> created at line 49.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007> created at line 49.
    Summary:
	inferred   2 Multiplexer(s).
Unit <communication> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 4
 1-bit latch                       : 4
# Multiplexers                     : 2
 1-bit 4-to-1 multiplexer          : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2170 - Unit communication : the following signal(s) form a combinatorial loop: clk.

Optimizing unit <communication> ...
Register <crd> equivalent to <WR> has been removed
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block communication, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : communication.ngr
Top Level Output File Name         : communication
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Multiplexers                     : 2
#      1-bit 4-to-1 multiplexer    : 2

Cell Usage :
# BELS                             : 3
#      GND                         : 1
#      INV                         : 1
#      LUT2_L                      : 1
# FlipFlops/Latches                : 3
#      LDE_1                       : 3
# IO Buffers                       : 11
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                       2  out of   1920     0%  
 Number of Slice Flip Flops:             3  out of   3840     0%  
 Number of 4 input LUTs:                 1  out of   3840     0%  
 Number of bonded IOBs:                 14  out of    173     8%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XST_GND:G                          | NONE                   | 3     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.633ns (Maximum Frequency: 379.795MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.184ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'XST_GND:G'
  Clock period: 2.633ns (frequency: 379.795MHz)
  Total number of paths / destination ports: 4 / 3
-------------------------------------------------------------------------
Delay:               2.633ns (Levels of Logic = 1)
  Source:            WR (LATCH)
  Destination:       cwr (LATCH)
  Source Clock:      XST_GND:G rising
  Destination Clock: XST_GND:G rising

  Data Path: WR to cwr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            3   0.633   1.246  WR (WR_OBUF)
     LUT2_L:I0->LO         1   0.551   0.000  _n00071 (_n0007)
     LDE_1:D                   0.203          cwr
    ----------------------------------------
    Total                      2.633ns (1.387ns logic, 1.246ns route)
                                       (52.7% logic, 47.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XST_GND:G'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              7.184ns (Levels of Logic = 1)
  Source:            WR (LATCH)
  Destination:       WR (PAD)
  Source Clock:      XST_GND:G rising

  Data Path: WR to WR
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            3   0.633   0.907  WR (WR_OBUF)
     OBUF:I->O                 5.644          WR_OBUF (WR)
    ----------------------------------------
    Total                      7.184ns (6.277ns logic, 0.907ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
CPU : 4.83 / 5.24 s | Elapsed : 5.00 / 5.00 s
 
--> 

Total memory usage is 97104 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   12 (   0 filtered)
Number of infos    :    3 (   0 filtered)