cancommunication.twr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise z:\work\speedmes\speedmes.ise -intstyle ise -e 3
-l 3 -s 4 -xml cancommunication cancommunication.ncd -o cancommunication.twr
cancommunication.pcf


Design file:              cancommunication.ncd
Physical constraint file: cancommunication.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
AD<0>       |    2.430(R)|   -0.476(R)|clk_BUFGP         |   0.000|
AD<1>       |    2.472(R)|   -0.509(R)|clk_BUFGP         |   0.000|
AD<2>       |    2.233(R)|   -0.318(R)|clk_BUFGP         |   0.000|
AD<3>       |    2.172(R)|   -0.269(R)|clk_BUFGP         |   0.000|
AD<4>       |    2.074(R)|   -0.190(R)|clk_BUFGP         |   0.000|
AD<5>       |    1.974(R)|   -0.110(R)|clk_BUFGP         |   0.000|
AD<6>       |    1.708(R)|    0.101(R)|clk_BUFGP         |   0.000|
AD<7>       |    1.797(R)|    0.031(R)|clk_BUFGP         |   0.000|
reset       |    9.305(R)|   -0.324(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
AD<0>       |    9.572(R)|clk_BUFGP         |   0.000|
AD<1>       |    9.930(R)|clk_BUFGP         |   0.000|
AD<2>       |    9.961(R)|clk_BUFGP         |   0.000|
AD<3>       |   10.320(R)|clk_BUFGP         |   0.000|
AD<4>       |    9.393(R)|clk_BUFGP         |   0.000|
AD<5>       |    9.954(R)|clk_BUFGP         |   0.000|
AD<6>       |    8.675(R)|clk_BUFGP         |   0.000|
AD<7>       |    9.425(R)|clk_BUFGP         |   0.000|
ALE         |    7.360(R)|clk_BUFGP         |   0.000|
CS          |    7.359(R)|clk_BUFGP         |   0.000|
RD          |    7.360(R)|clk_BUFGP         |   0.000|
STATUS<0>   |    7.360(R)|clk_BUFGP         |   0.000|
STATUS<1>   |    7.360(R)|clk_BUFGP         |   0.000|
STATUS<2>   |    7.360(R)|clk_BUFGP         |   0.000|
STATUS<3>   |    7.359(R)|clk_BUFGP         |   0.000|
STATUS<4>   |    7.360(R)|clk_BUFGP         |   0.000|
STATUS<5>   |    7.359(R)|clk_BUFGP         |   0.000|
STATUS<6>   |    7.359(R)|clk_BUFGP         |   0.000|
STATUS<7>   |    7.359(R)|clk_BUFGP         |   0.000|
WR          |    7.360(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   16.690|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Nov 22 18:03:22 2005
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Peak Memory Usage: 83 MB