cancommunication_timesim.vhd

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

      I1 => staterw_8_CYSELF,
      O => staterw_8_CYAND
    );
  staterw_8_CYMUXFAST_70 : X_MUX2
    port map (
      IA => staterw_8_CYMUXG2,
      IB => staterw_8_FASTCARRY,
      SEL => staterw_8_CYAND,
      O => staterw_8_CYMUXFAST
    );
  staterw_8_CYMUXG2_71 : X_MUX2
    port map (
      IA => staterw_8_LOGIC_ZERO,
      IB => staterw_8_CYMUXF2,
      SEL => staterw_8_CYSELG,
      O => staterw_8_CYMUXG2
    );
  staterw_8_CYSELG_72 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_9_1_O,
      O => staterw_8_CYSELG
    );
  staterw_8_SRINV_73 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_8_SRINV
    );
  staterw_8_CLKINV_74 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_8_CLKINV
    );
  staterw_8_CEINV_75 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_8_CEINV
    );
  Q_n0043_9_1 : X_LUT4
    generic map(
      INIT => X"B800"
    )
    port map (
      ADR0 => N65,
      ADR1 => Q_n0066,
      ADR2 => N769_0,
      ADR3 => N80,
      O => Q_n0043_9_1_O
    );
  staterw_10_LOGIC_ZERO_76 : X_ZERO
    port map (
      O => staterw_10_LOGIC_ZERO
    );
  staterw_10_DXMUX_77 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_10_XORF,
      O => staterw_10_DXMUX
    );
  staterw_10_XORF_78 : X_XOR2
    port map (
      I0 => staterw_10_CYINIT,
      I1 => Q_n0043_10_1_O,
      O => staterw_10_XORF
    );
  staterw_10_CYMUXF : X_MUX2
    port map (
      IA => staterw_10_LOGIC_ZERO,
      IB => staterw_10_CYINIT,
      SEL => staterw_10_CYSELF,
      O => cancommunication_n0032_10_cyo
    );
  staterw_10_CYMUXF2_79 : X_MUX2
    port map (
      IA => staterw_10_LOGIC_ZERO,
      IB => staterw_10_LOGIC_ZERO,
      SEL => staterw_10_CYSELF,
      O => staterw_10_CYMUXF2
    );
  staterw_10_CYINIT_80 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_9_cyo,
      O => staterw_10_CYINIT
    );
  staterw_10_CYSELF_81 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_10_1_O,
      O => staterw_10_CYSELF
    );
  staterw_10_DYMUX_82 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_10_XORG,
      O => staterw_10_DYMUX
    );
  staterw_10_XORG_83 : X_XOR2
    port map (
      I0 => cancommunication_n0032_10_cyo,
      I1 => Q_n0043_11_1_O,
      O => staterw_10_XORG
    );
  staterw_10_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_10_CYMUXFAST,
      O => cancommunication_n0032_11_cyo
    );
  staterw_10_FASTCARRY_84 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_9_cyo,
      O => staterw_10_FASTCARRY
    );
  staterw_10_CYAND_85 : X_AND2
    port map (
      I0 => staterw_10_CYSELG,
      I1 => staterw_10_CYSELF,
      O => staterw_10_CYAND
    );
  staterw_10_CYMUXFAST_86 : X_MUX2
    port map (
      IA => staterw_10_CYMUXG2,
      IB => staterw_10_FASTCARRY,
      SEL => staterw_10_CYAND,
      O => staterw_10_CYMUXFAST
    );
  staterw_10_CYMUXG2_87 : X_MUX2
    port map (
      IA => staterw_10_LOGIC_ZERO,
      IB => staterw_10_CYMUXF2,
      SEL => staterw_10_CYSELG,
      O => staterw_10_CYMUXG2
    );
  staterw_10_CYSELG_88 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_11_1_O,
      O => staterw_10_CYSELG
    );
  staterw_10_SRINV_89 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_10_SRINV
    );
  staterw_10_CLKINV_90 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_10_CLKINV
    );
  staterw_10_CEINV_91 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_10_CEINV
    );
  staterw_12_LOGIC_ZERO_92 : X_ZERO
    port map (
      O => staterw_12_LOGIC_ZERO
    );
  staterw_12_DXMUX_93 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_12_XORF,
      O => staterw_12_DXMUX
    );
  staterw_12_XORF_94 : X_XOR2
    port map (
      I0 => staterw_12_CYINIT,
      I1 => Q_n0043_12_1_O,
      O => staterw_12_XORF
    );
  staterw_12_CYMUXF : X_MUX2
    port map (
      IA => staterw_12_LOGIC_ZERO,
      IB => staterw_12_CYINIT,
      SEL => staterw_12_CYSELF,
      O => cancommunication_n0032_12_cyo
    );
  staterw_12_CYMUXF2_95 : X_MUX2
    port map (
      IA => staterw_12_LOGIC_ZERO,
      IB => staterw_12_LOGIC_ZERO,
      SEL => staterw_12_CYSELF,
      O => staterw_12_CYMUXF2
    );
  staterw_12_CYINIT_96 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_11_cyo,
      O => staterw_12_CYINIT
    );
  staterw_12_CYSELF_97 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_12_1_O,
      O => staterw_12_CYSELF
    );
  staterw_12_DYMUX_98 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_12_XORG,
      O => staterw_12_DYMUX
    );
  staterw_12_XORG_99 : X_XOR2
    port map (
      I0 => cancommunication_n0032_12_cyo,
      I1 => Q_n0043_13_1_O,
      O => staterw_12_XORG
    );
  staterw_12_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_12_CYMUXFAST,
      O => cancommunication_n0032_13_cyo
    );
  staterw_12_FASTCARRY_100 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_11_cyo,
      O => staterw_12_FASTCARRY
    );
  staterw_12_CYAND_101 : X_AND2
    port map (
      I0 => staterw_12_CYSELG,
      I1 => staterw_12_CYSELF,
      O => staterw_12_CYAND
    );
  staterw_12_CYMUXFAST_102 : X_MUX2
    port map (
      IA => staterw_12_CYMUXG2,
      IB => staterw_12_FASTCARRY,
      SEL => staterw_12_CYAND,
      O => staterw_12_CYMUXFAST
    );
  staterw_12_CYMUXG2_103 : X_MUX2
    port map (
      IA => staterw_12_LOGIC_ZERO,
      IB => staterw_12_CYMUXF2,
      SEL => staterw_12_CYSELG,
      O => staterw_12_CYMUXG2
    );
  staterw_12_CYSELG_104 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_13_1_O,
      O => staterw_12_CYSELG
    );
  staterw_12_SRINV_105 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_12_SRINV
    );
  staterw_12_CLKINV_106 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_12_CLKINV
    );
  staterw_12_CEINV_107 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_12_CEINV
    );
  Q_n0043_13_1 : X_LUT4
    generic map(
      INIT => X"88A0"
    )
    port map (
      ADR0 => N80,
      ADR1 => N65,
      ADR2 => N777_0,
      ADR3 => Q_n0066,
      O => Q_n0043_13_1_O
    );
  staterw_14_LOGIC_ZERO_108 : X_ZERO
    port map (
      O => staterw_14_LOGIC_ZERO
    );
  staterw_14_DXMUX_109 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_14_XORF,
      O => staterw_14_DXMUX
    );
  staterw_14_XORF_110 : X_XOR2
    port map (
      I0 => staterw_14_CYINIT,
      I1 => Q_n0043_14_1_O,
      O => staterw_14_XORF
    );
  staterw_14_CYMUXF : X_MUX2
    port map (
      IA => staterw_14_LOGIC_ZERO,
      IB => staterw_14_CYINIT,
      SEL => staterw_14_CYSELF,
      O => cancommunication_n0032_14_cyo
    );
  staterw_14_CYMUXF2_111 : X_MUX2
    port map (
      IA => staterw_14_LOGIC_ZERO,
      IB => staterw_14_LOGIC_ZERO,
      SEL => staterw_14_CYSELF,
      O => staterw_14_CYMUXF2
    );
  staterw_14_CYINIT_112 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_13_cyo,
      O => staterw_14_CYINIT
    );
  staterw_14_CYSELF_113 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_14_1_O,
      O => staterw_14_CYSELF
    );
  staterw_14_DYMUX_114 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_14_XORG,
      O => staterw_14_DYMUX
    );
  staterw_14_XORG_115 : X_XOR2
    port map (
      I0 => cancommunication_n0032_14_cyo,
      I1 => Q_n0043_15_1_O,
      O => staterw_14_XORG
    );
  staterw_14_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_14_CYMUXFAST,
      O => cancommunication_n0032_15_cyo
    );
  staterw_14_FASTCARRY_116 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_13_cyo,
      O => staterw_14_FASTCARRY
    );
  staterw_14_CYAND_117 : X_AND2
    port map (
      I0 => staterw_14_CYSELG,
      I1 => staterw_14_CYSELF,
      O => staterw_14_CYAND
    );
  staterw_14_CYMUXFAST_118 : X_MUX2
    port map (
      IA => staterw_14_CYMUXG2,
      IB => staterw_14_FASTCARRY,
      SEL => staterw_14_CYAND,
      O => staterw_14_CYMUXFAST
    );
  staterw_14_CYMUXG2_119 : X_MUX2
    port map (
      IA => staterw_14_LOGIC_ZERO,
      IB => staterw_14_CYMUXF2,
      SEL => staterw_14_CYSELG,
      O => staterw_14_CYMUXG2
    );
  staterw_14_CYSELG_120 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_15_1_O,
      O => staterw_14_CYSELG
    );
  staterw_14_SRINV_121 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_14_SRINV
    );
  staterw_14_CLKINV_122 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_14_CLKINV
    );
  staterw_14_CEINV_123 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_14_CEINV
    );
  N783_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N783,
      O => N783_0
    );
  N783_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N65_pack_1,
      O => N65
    );
  Ker65_124 : X_LUT4
    generic map(
      INIT => X"4500"
    )
    port map (
      ADR0 => Q_n0069,
      ADR1 => N182_0,
      ADR2 => N77_0,
      ADR3 => CHOICE110,
      O => N65_pack_1
    );
  N735_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N735,
      O => N735_0