cancommunication_timesim.vhd

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

      I => staterw_2_XORF,
      O => staterw_2_DXMUX
    );
  staterw_2_XORF_14 : X_XOR2
    port map (
      I0 => staterw_2_CYINIT,
      I1 => Q_n0043_2_1_O,
      O => staterw_2_XORF
    );
  staterw_2_CYMUXF : X_MUX2
    port map (
      IA => staterw_2_LOGIC_ZERO,
      IB => staterw_2_CYINIT,
      SEL => staterw_2_CYSELF,
      O => cancommunication_n0032_2_cyo
    );
  staterw_2_CYMUXF2_15 : X_MUX2
    port map (
      IA => staterw_2_LOGIC_ZERO,
      IB => staterw_2_LOGIC_ZERO,
      SEL => staterw_2_CYSELF,
      O => staterw_2_CYMUXF2
    );
  staterw_2_CYINIT_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_1_cyo,
      O => staterw_2_CYINIT
    );
  staterw_2_CYSELF_17 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_2_1_O,
      O => staterw_2_CYSELF
    );
  staterw_2_DYMUX_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_2_XORG,
      O => staterw_2_DYMUX
    );
  staterw_2_XORG_19 : X_XOR2
    port map (
      I0 => cancommunication_n0032_2_cyo,
      I1 => Q_n0043_3_O,
      O => staterw_2_XORG
    );
  staterw_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_2_CYMUXFAST,
      O => cancommunication_n0032_3_cyo
    );
  staterw_2_FASTCARRY_20 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_1_cyo,
      O => staterw_2_FASTCARRY
    );
  staterw_2_CYAND_21 : X_AND2
    port map (
      I0 => staterw_2_CYSELG,
      I1 => staterw_2_CYSELF,
      O => staterw_2_CYAND
    );
  staterw_2_CYMUXFAST_22 : X_MUX2
    port map (
      IA => staterw_2_CYMUXG2,
      IB => staterw_2_FASTCARRY,
      SEL => staterw_2_CYAND,
      O => staterw_2_CYMUXFAST
    );
  staterw_2_CYMUXG2_23 : X_MUX2
    port map (
      IA => staterw_2_LOGIC_ZERO,
      IB => staterw_2_CYMUXF2,
      SEL => staterw_2_CYSELG,
      O => staterw_2_CYMUXG2
    );
  staterw_2_CYSELG_24 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_3_O,
      O => staterw_2_CYSELG
    );
  staterw_2_SRINV_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_2_SRINV
    );
  staterw_2_CLKINV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_2_CLKINV
    );
  staterw_2_CEINV_27 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_2_CEINV
    );
  Q_n0043_3_Q : X_LUT4
    generic map(
      INIT => X"C044"
    )
    port map (
      ADR0 => N789_0,
      ADR1 => N80,
      ADR2 => N790_0,
      ADR3 => N65,
      O => Q_n0043_3_O
    );
  staterw_4_LOGIC_ZERO_28 : X_ZERO
    port map (
      O => staterw_4_LOGIC_ZERO
    );
  staterw_4_DXMUX_29 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_4_XORF,
      O => staterw_4_DXMUX
    );
  staterw_4_XORF_30 : X_XOR2
    port map (
      I0 => staterw_4_CYINIT,
      I1 => Q_n0043_4_1_O,
      O => staterw_4_XORF
    );
  staterw_4_CYMUXF : X_MUX2
    port map (
      IA => staterw_4_LOGIC_ZERO,
      IB => staterw_4_CYINIT,
      SEL => staterw_4_CYSELF,
      O => cancommunication_n0032_4_cyo
    );
  staterw_4_CYMUXF2_31 : X_MUX2
    port map (
      IA => staterw_4_LOGIC_ZERO,
      IB => staterw_4_LOGIC_ZERO,
      SEL => staterw_4_CYSELF,
      O => staterw_4_CYMUXF2
    );
  staterw_4_CYINIT_32 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_3_cyo,
      O => staterw_4_CYINIT
    );
  staterw_4_CYSELF_33 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_4_1_O,
      O => staterw_4_CYSELF
    );
  staterw_4_DYMUX_34 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_4_XORG,
      O => staterw_4_DYMUX
    );
  staterw_4_XORG_35 : X_XOR2
    port map (
      I0 => cancommunication_n0032_4_cyo,
      I1 => Q_n0043_5_1_O,
      O => staterw_4_XORG
    );
  staterw_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_4_CYMUXFAST,
      O => cancommunication_n0032_5_cyo
    );
  staterw_4_FASTCARRY_36 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_3_cyo,
      O => staterw_4_FASTCARRY
    );
  staterw_4_CYAND_37 : X_AND2
    port map (
      I0 => staterw_4_CYSELG,
      I1 => staterw_4_CYSELF,
      O => staterw_4_CYAND
    );
  staterw_4_CYMUXFAST_38 : X_MUX2
    port map (
      IA => staterw_4_CYMUXG2,
      IB => staterw_4_FASTCARRY,
      SEL => staterw_4_CYAND,
      O => staterw_4_CYMUXFAST
    );
  staterw_4_CYMUXG2_39 : X_MUX2
    port map (
      IA => staterw_4_LOGIC_ZERO,
      IB => staterw_4_CYMUXF2,
      SEL => staterw_4_CYSELG,
      O => staterw_4_CYMUXG2
    );
  staterw_4_CYSELG_40 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_5_1_O,
      O => staterw_4_CYSELG
    );
  staterw_4_SRINV_41 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_4_SRINV
    );
  staterw_4_CLKINV_42 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_4_CLKINV
    );
  staterw_4_CEINV_43 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_4_CEINV
    );
  Q_n0043_5_1 : X_LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      ADR0 => N80,
      ADR1 => Q_n0066,
      ADR2 => N761_0,
      ADR3 => N65,
      O => Q_n0043_5_1_O
    );
  staterw_6_LOGIC_ZERO_44 : X_ZERO
    port map (
      O => staterw_6_LOGIC_ZERO
    );
  staterw_6_DXMUX_45 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_6_XORF,
      O => staterw_6_DXMUX
    );
  staterw_6_XORF_46 : X_XOR2
    port map (
      I0 => staterw_6_CYINIT,
      I1 => Q_n0043_6_1_O,
      O => staterw_6_XORF
    );
  staterw_6_CYMUXF : X_MUX2
    port map (
      IA => staterw_6_LOGIC_ZERO,
      IB => staterw_6_CYINIT,
      SEL => staterw_6_CYSELF,
      O => cancommunication_n0032_6_cyo
    );
  staterw_6_CYMUXF2_47 : X_MUX2
    port map (
      IA => staterw_6_LOGIC_ZERO,
      IB => staterw_6_LOGIC_ZERO,
      SEL => staterw_6_CYSELF,
      O => staterw_6_CYMUXF2
    );
  staterw_6_CYINIT_48 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_5_cyo,
      O => staterw_6_CYINIT
    );
  staterw_6_CYSELF_49 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_6_1_O,
      O => staterw_6_CYSELF
    );
  staterw_6_DYMUX_50 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_6_XORG,
      O => staterw_6_DYMUX
    );
  staterw_6_XORG_51 : X_XOR2
    port map (
      I0 => cancommunication_n0032_6_cyo,
      I1 => Q_n0043_7_1_O,
      O => staterw_6_XORG
    );
  staterw_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_6_CYMUXFAST,
      O => cancommunication_n0032_7_cyo
    );
  staterw_6_FASTCARRY_52 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_5_cyo,
      O => staterw_6_FASTCARRY
    );
  staterw_6_CYAND_53 : X_AND2
    port map (
      I0 => staterw_6_CYSELG,
      I1 => staterw_6_CYSELF,
      O => staterw_6_CYAND
    );
  staterw_6_CYMUXFAST_54 : X_MUX2
    port map (
      IA => staterw_6_CYMUXG2,
      IB => staterw_6_FASTCARRY,
      SEL => staterw_6_CYAND,
      O => staterw_6_CYMUXFAST
    );
  staterw_6_CYMUXG2_55 : X_MUX2
    port map (
      IA => staterw_6_LOGIC_ZERO,
      IB => staterw_6_CYMUXF2,
      SEL => staterw_6_CYSELG,
      O => staterw_6_CYMUXG2
    );
  staterw_6_CYSELG_56 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_7_1_O,
      O => staterw_6_CYSELG
    );
  staterw_6_SRINV_57 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_6_SRINV
    );
  staterw_6_CLKINV_58 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_6_CLKINV
    );
  staterw_6_CEINV_59 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_6_CEINV
    );
  Q_n0043_7_1 : X_LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      ADR0 => N80,
      ADR1 => Q_n0066,
      ADR2 => N765_0,
      ADR3 => N65,
      O => Q_n0043_7_1_O
    );
  staterw_8_LOGIC_ZERO_60 : X_ZERO
    port map (
      O => staterw_8_LOGIC_ZERO
    );
  staterw_8_DXMUX_61 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_8_XORF,
      O => staterw_8_DXMUX
    );
  staterw_8_XORF_62 : X_XOR2
    port map (
      I0 => staterw_8_CYINIT,
      I1 => Q_n0043_8_1_O,
      O => staterw_8_XORF
    );
  staterw_8_CYMUXF : X_MUX2
    port map (
      IA => staterw_8_LOGIC_ZERO,
      IB => staterw_8_CYINIT,
      SEL => staterw_8_CYSELF,
      O => cancommunication_n0032_8_cyo
    );
  staterw_8_CYMUXF2_63 : X_MUX2
    port map (
      IA => staterw_8_LOGIC_ZERO,
      IB => staterw_8_LOGIC_ZERO,
      SEL => staterw_8_CYSELF,
      O => staterw_8_CYMUXF2
    );
  staterw_8_CYINIT_64 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_7_cyo,
      O => staterw_8_CYINIT
    );
  staterw_8_CYSELF_65 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_8_1_O,
      O => staterw_8_CYSELF
    );
  staterw_8_DYMUX_66 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_8_XORG,
      O => staterw_8_DYMUX
    );
  staterw_8_XORG_67 : X_XOR2
    port map (
      I0 => cancommunication_n0032_8_cyo,
      I1 => Q_n0043_9_1_O,
      O => staterw_8_XORG
    );
  staterw_8_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_8_CYMUXFAST,
      O => cancommunication_n0032_9_cyo
    );
  staterw_8_FASTCARRY_68 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cancommunication_n0032_7_cyo,
      O => staterw_8_FASTCARRY
    );
  staterw_8_CYAND_69 : X_AND2
    port map (
      I0 => staterw_8_CYSELG,