cancommunication_timesim.vhd

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

  signal WR_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal RD_ENABLE : STD_LOGIC; 
  signal RD_O : STD_LOGIC; 
  signal RD_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal RD_OBUF : STD_LOGIC; 
  signal RD_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal RD_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_0_ENABLE : STD_LOGIC; 
  signal AD_0_GTS_OR_T : STD_LOGIC; 
  signal AD_0_O : STD_LOGIC; 
  signal AD_0_T : STD_LOGIC; 
  signal AD_0_INBUF : STD_LOGIC; 
  signal AD_1_ENABLE : STD_LOGIC; 
  signal AD_1_GTS_OR_T : STD_LOGIC; 
  signal AD_1_O : STD_LOGIC; 
  signal AD_1_T : STD_LOGIC; 
  signal AD_1_INBUF : STD_LOGIC; 
  signal AD_2_ENABLE : STD_LOGIC; 
  signal AD_2_GTS_OR_T : STD_LOGIC; 
  signal AD_2_O : STD_LOGIC; 
  signal AD_2_T : STD_LOGIC; 
  signal AD_2_INBUF : STD_LOGIC; 
  signal AD_3_ENABLE : STD_LOGIC; 
  signal AD_3_GTS_OR_T : STD_LOGIC; 
  signal AD_3_O : STD_LOGIC; 
  signal AD_3_T : STD_LOGIC; 
  signal AD_3_INBUF : STD_LOGIC; 
  signal AD_4_ENABLE : STD_LOGIC; 
  signal AD_4_GTS_OR_T : STD_LOGIC; 
  signal AD_4_O : STD_LOGIC; 
  signal AD_4_T : STD_LOGIC; 
  signal AD_4_INBUF : STD_LOGIC; 
  signal AD_5_ENABLE : STD_LOGIC; 
  signal AD_5_GTS_OR_T : STD_LOGIC; 
  signal AD_5_O : STD_LOGIC; 
  signal AD_5_T : STD_LOGIC; 
  signal AD_5_INBUF : STD_LOGIC; 
  signal AD_6_ENABLE : STD_LOGIC; 
  signal AD_6_GTS_OR_T : STD_LOGIC; 
  signal AD_6_O : STD_LOGIC; 
  signal AD_6_T : STD_LOGIC; 
  signal AD_6_INBUF : STD_LOGIC; 
  signal reset_INBUF : STD_LOGIC; 
  signal AD_7_ENABLE : STD_LOGIC; 
  signal AD_7_GTS_OR_T : STD_LOGIC; 
  signal AD_7_O : STD_LOGIC; 
  signal AD_7_T : STD_LOGIC; 
  signal AD_7_INBUF : STD_LOGIC; 
  signal ALE_ENABLE : STD_LOGIC; 
  signal ALE_O : STD_LOGIC; 
  signal ALE_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal ALE_OBUF : STD_LOGIC; 
  signal ALE_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal ALE_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal staterw_16_DXMUX : STD_LOGIC; 
  signal staterw_16_XORF : STD_LOGIC; 
  signal staterw_16_CYINIT : STD_LOGIC; 
  signal Q_n0043_16_1_O : STD_LOGIC; 
  signal staterw_16_DYMUX : STD_LOGIC; 
  signal staterw_16_XORG : STD_LOGIC; 
  signal cancommunication_n0032_16_cyo : STD_LOGIC; 
  signal staterw_16_CYSELF : STD_LOGIC; 
  signal staterw_16_CYMUXFAST : STD_LOGIC; 
  signal staterw_16_CYAND : STD_LOGIC; 
  signal staterw_16_FASTCARRY : STD_LOGIC; 
  signal staterw_16_CYMUXG2 : STD_LOGIC; 
  signal staterw_16_CYMUXF2 : STD_LOGIC; 
  signal staterw_16_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_16_CYSELG : STD_LOGIC; 
  signal Q_n0043_17_1_O : STD_LOGIC; 
  signal staterw_16_SRINV : STD_LOGIC; 
  signal staterw_16_CLKINV : STD_LOGIC; 
  signal staterw_16_CEINV : STD_LOGIC; 
  signal staterw_18_DXMUX : STD_LOGIC; 
  signal staterw_18_XORF : STD_LOGIC; 
  signal staterw_18_CYINIT : STD_LOGIC; 
  signal Q_n0043_18_1_O : STD_LOGIC; 
  signal staterw_18_DYMUX : STD_LOGIC; 
  signal staterw_18_XORG : STD_LOGIC; 
  signal cancommunication_n0032_18_cyo : STD_LOGIC; 
  signal staterw_18_CYSELF : STD_LOGIC; 
  signal staterw_18_CYMUXFAST : STD_LOGIC; 
  signal staterw_18_CYAND : STD_LOGIC; 
  signal staterw_18_FASTCARRY : STD_LOGIC; 
  signal staterw_18_CYMUXG2 : STD_LOGIC; 
  signal staterw_18_CYMUXF2 : STD_LOGIC; 
  signal staterw_18_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_18_CYSELG : STD_LOGIC; 
  signal Q_n0043_19_1_O : STD_LOGIC; 
  signal staterw_18_SRINV : STD_LOGIC; 
  signal staterw_18_CLKINV : STD_LOGIC; 
  signal staterw_18_CEINV : STD_LOGIC; 
  signal staterw_20_DXMUX : STD_LOGIC; 
  signal staterw_20_XORF : STD_LOGIC; 
  signal staterw_20_CYINIT : STD_LOGIC; 
  signal Q_n0043_20_1_O : STD_LOGIC; 
  signal staterw_20_DYMUX : STD_LOGIC; 
  signal staterw_20_XORG : STD_LOGIC; 
  signal cancommunication_n0032_20_cyo : STD_LOGIC; 
  signal staterw_20_CYSELF : STD_LOGIC; 
  signal staterw_20_CYMUXFAST : STD_LOGIC; 
  signal staterw_20_CYAND : STD_LOGIC; 
  signal staterw_20_FASTCARRY : STD_LOGIC; 
  signal staterw_20_CYMUXG2 : STD_LOGIC; 
  signal staterw_20_CYMUXF2 : STD_LOGIC; 
  signal staterw_20_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_20_CYSELG : STD_LOGIC; 
  signal Q_n0043_21_1_O : STD_LOGIC; 
  signal staterw_20_SRINV : STD_LOGIC; 
  signal staterw_20_CLKINV : STD_LOGIC; 
  signal staterw_20_CEINV : STD_LOGIC; 
  signal staterw_22_DXMUX : STD_LOGIC; 
  signal staterw_22_XORF : STD_LOGIC; 
  signal staterw_22_CYINIT : STD_LOGIC; 
  signal Q_n0043_22_1_O : STD_LOGIC; 
  signal staterw_22_DYMUX : STD_LOGIC; 
  signal staterw_22_XORG : STD_LOGIC; 
  signal cancommunication_n0032_22_cyo : STD_LOGIC; 
  signal staterw_22_CYSELF : STD_LOGIC; 
  signal staterw_22_CYMUXFAST : STD_LOGIC; 
  signal staterw_22_CYAND : STD_LOGIC; 
  signal staterw_22_FASTCARRY : STD_LOGIC; 
  signal staterw_22_CYMUXG2 : STD_LOGIC; 
  signal staterw_22_CYMUXF2 : STD_LOGIC; 
  signal staterw_22_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_22_CYSELG : STD_LOGIC; 
  signal Q_n0043_23_1_O : STD_LOGIC; 
  signal staterw_22_SRINV : STD_LOGIC; 
  signal staterw_22_CLKINV : STD_LOGIC; 
  signal staterw_22_CEINV : STD_LOGIC; 
  signal staterw_24_DXMUX : STD_LOGIC; 
  signal staterw_24_XORF : STD_LOGIC; 
  signal staterw_24_CYINIT : STD_LOGIC; 
  signal Q_n0043_24_1_O : STD_LOGIC; 
  signal staterw_24_DYMUX : STD_LOGIC; 
  signal staterw_24_XORG : STD_LOGIC; 
  signal cancommunication_n0032_24_cyo : STD_LOGIC; 
  signal staterw_24_CYSELF : STD_LOGIC; 
  signal staterw_24_CYMUXFAST : STD_LOGIC; 
  signal staterw_24_CYAND : STD_LOGIC; 
  signal staterw_24_FASTCARRY : STD_LOGIC; 
  signal staterw_24_CYMUXG2 : STD_LOGIC; 
  signal staterw_24_CYMUXF2 : STD_LOGIC; 
  signal staterw_24_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_24_CYSELG : STD_LOGIC; 
  signal Q_n0043_25_1_O : STD_LOGIC; 
  signal staterw_24_SRINV : STD_LOGIC; 
  signal staterw_24_CLKINV : STD_LOGIC; 
  signal staterw_24_CEINV : STD_LOGIC; 
  signal staterw_26_DXMUX : STD_LOGIC; 
  signal staterw_26_XORF : STD_LOGIC; 
  signal staterw_26_CYINIT : STD_LOGIC; 
  signal Q_n0043_26_1_O : STD_LOGIC; 
  signal staterw_26_DYMUX : STD_LOGIC; 
  signal staterw_26_XORG : STD_LOGIC; 
  signal cancommunication_n0032_26_cyo : STD_LOGIC; 
  signal staterw_26_CYSELF : STD_LOGIC; 
  signal staterw_26_CYMUXFAST : STD_LOGIC; 
  signal staterw_26_CYAND : STD_LOGIC; 
  signal staterw_26_FASTCARRY : STD_LOGIC; 
  signal staterw_26_CYMUXG2 : STD_LOGIC; 
  signal staterw_26_CYMUXF2 : STD_LOGIC; 
  signal staterw_26_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_26_CYSELG : STD_LOGIC; 
  signal Q_n0043_27_1_O : STD_LOGIC; 
  signal staterw_26_SRINV : STD_LOGIC; 
  signal staterw_26_CLKINV : STD_LOGIC; 
  signal staterw_26_CEINV : STD_LOGIC; 
  signal staterw_28_DXMUX : STD_LOGIC; 
  signal staterw_28_XORF : STD_LOGIC; 
  signal staterw_28_CYINIT : STD_LOGIC; 
  signal Q_n0043_28_1_O : STD_LOGIC; 
  signal staterw_28_DYMUX : STD_LOGIC; 
  signal staterw_28_XORG : STD_LOGIC; 
  signal cancommunication_n0032_28_cyo : STD_LOGIC; 
  signal staterw_28_CYSELF : STD_LOGIC; 
  signal staterw_28_CYMUXFAST : STD_LOGIC; 
  signal staterw_28_CYAND : STD_LOGIC; 
  signal staterw_28_FASTCARRY : STD_LOGIC; 
  signal staterw_28_CYMUXG2 : STD_LOGIC; 
  signal staterw_28_CYMUXF2 : STD_LOGIC; 
  signal staterw_28_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_28_CYSELG : STD_LOGIC; 
  signal Q_n0043_29_1_O : STD_LOGIC; 
  signal staterw_28_SRINV : STD_LOGIC; 
  signal staterw_28_CLKINV : STD_LOGIC; 
  signal staterw_28_CEINV : STD_LOGIC; 
  signal CHOICE49 : STD_LOGIC; 
  signal address_4_DYMUX : STD_LOGIC; 
  signal address_4_GYMUX : STD_LOGIC; 
  signal state_FFd1_In : STD_LOGIC; 
  signal address_4_CLKINV : STD_LOGIC; 
  signal address_4_CEINV : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal state_FFd4_DYMUX : STD_LOGIC; 
  signal state_FFd4_In : STD_LOGIC; 
  signal state_FFd4_SRINV : STD_LOGIC; 
  signal state_FFd4_CLKINV : STD_LOGIC; 
  signal state_FFd4_CEINV : STD_LOGIC; 
  signal Q_n0183 : STD_LOGIC; 
  signal mode_0_DYMUX : STD_LOGIC; 
  signal mode_0_GYMUX : STD_LOGIC; 
  signal mode_0_SRINV : STD_LOGIC; 
  signal mode_0_CLKINV : STD_LOGIC; 
  signal mode_0_CEINV : STD_LOGIC; 
  signal oldmode_1_DXMUX : STD_LOGIC; 
  signal oldmode_1_DYMUX : STD_LOGIC; 
  signal oldmode_1_CLKINV : STD_LOGIC; 
  signal oldmode_1_CEINV : STD_LOGIC; 
  signal mode_2_1_DXMUX : STD_LOGIC; 
  signal mode_2_1_FXMUX : STD_LOGIC; 
  signal N7_pack_1 : STD_LOGIC; 
  signal mode_2_1_SRINV : STD_LOGIC; 
  signal mode_2_1_CLKINV : STD_LOGIC; 
  signal mode_2_1_CEINV : STD_LOGIC; 
  signal Q_n0030_5_1_O : STD_LOGIC; 
  signal Q_n0030_7_1_O : STD_LOGIC; 
  signal N806 : STD_LOGIC; 
  signal N755 : STD_LOGIC; 
  signal N749 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal Q_n0037 : STD_LOGIC; 
  signal N779 : STD_LOGIC; 
  signal N767 : STD_LOGIC; 
  signal Q_n0187 : STD_LOGIC; 
  signal CHOICE123_pack_1 : STD_LOGIC; 
  signal N737 : STD_LOGIC; 
  signal N802 : STD_LOGIC; 
  signal Q_n0175 : STD_LOGIC; 
  signal CHOICE133 : STD_LOGIC; 
  signal N781 : STD_LOGIC; 
  signal N777 : STD_LOGIC; 
  signal state_FFd1_DXMUX : STD_LOGIC; 
  signal CHOICE15 : STD_LOGIC; 
  signal state_FFd1_DYMUX : STD_LOGIC; 
  signal state_FFd1_SRINV : STD_LOGIC; 
  signal state_FFd1_CLKINV : STD_LOGIC; 
  signal state_FFd1_CEINV : STD_LOGIC; 
  signal N789 : STD_LOGIC; 
  signal CHOICE147 : STD_LOGIC; 
  signal N773 : STD_LOGIC; 
  signal N771 : STD_LOGIC; 
  signal CHOICE115 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal mode_2_DYMUX : STD_LOGIC; 
  signal mode_2_SRINV : STD_LOGIC; 
  signal mode_2_CLKINV : STD_LOGIC; 
  signal mode_2_CEINV : STD_LOGIC; 
  signal N47 : STD_LOGIC; 
  signal CHOICE77 : STD_LOGIC; 
  signal N63_pack_1 : STD_LOGIC; 
  signal N763 : STD_LOGIC; 
  signal N765 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal CHOICE214 : STD_LOGIC; 
  signal CHOICE69 : STD_LOGIC; 
  signal N68 : STD_LOGIC; 
  signal N182 : STD_LOGIC; 
  signal N148 : STD_LOGIC; 
  signal N78 : STD_LOGIC; 
  signal N769 : STD_LOGIC; 
  signal CHOICE221 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal state_FFd3_DXMUX : STD_LOGIC; 
  signal state_FFd3_In : STD_LOGIC; 
  signal N804_pack_1 : STD_LOGIC; 
  signal state_FFd3_SRINV : STD_LOGIC; 
  signal state_FFd3_CLKINV : STD_LOGIC; 
  signal state_FFd3_CEINV : STD_LOGIC; 
  signal address_3_DXMUX : STD_LOGIC; 
  signal N96_pack_1 : STD_LOGIC; 
  signal address_3_CLKINV : STD_LOGIC; 
  signal address_3_CEINV : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N775 : STD_LOGIC; 
  signal N785 : STD_LOGIC; 
  signal CHOICE206 : STD_LOGIC; 
  signal CHOICE199 : STD_LOGIC; 
  signal data_0_DXMUX : STD_LOGIC; 
  signal CHOICE6_pack_1 : STD_LOGIC; 
  signal data_0_CLKINV : STD_LOGIC; 
  signal data_0_CEINV : STD_LOGIC; 
  signal Q_n0030_4_1_O : STD_LOGIC; 
  signal Q_n0030_0_1_O : STD_LOGIC; 
  signal Q_n0030_3_1_O : STD_LOGIC; 
  signal CHOICE62 : STD_LOGIC; 
  signal Q_n0030_2_1_O : STD_LOGIC; 
  signal Q_n0030_1_1_O : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal CHOICE80 : STD_LOGIC; 
  signal N792 : STD_LOGIC; 
  signal mode_1_DXMUX : STD_LOGIC; 
  signal mode_1_FXMUX : STD_LOGIC; 
  signal N103_pack_1 : STD_LOGIC; 
  signal mode_1_SRINV : STD_LOGIC; 
  signal mode_1_CLKINV : STD_LOGIC; 
  signal mode_1_CEINV : STD_LOGIC; 
  signal Q_n0186 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal mode_0_1_DYMUX : STD_LOGIC; 
  signal mode_0_1_SRINV : STD_LOGIC; 
  signal mode_0_1_CLKINV : STD_LOGIC; 
  signal mode_0_1_CEINV : STD_LOGIC; 
  signal mode_1_1_DYMUX : STD_LOGIC; 
  signal mode_1_1_SRINV : STD_LOGIC; 
  signal mode_1_1_CLKINV : STD_LOGIC; 
  signal mode_1_1_CEINV : STD_LOGIC; 
  signal WR_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal RD_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_3_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_4_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_5_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_6_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal AD_7_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal ALE_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_0_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_0_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_1_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_2_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_2_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_3_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_3_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_4_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_4_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_4_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_5_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_5_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_5_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal data_2_FFX_RST : STD_LOGIC; 
  signal data_4_FFX_RST : STD_LOGIC; 
  signal data_6_FFX_RST : STD_LOGIC; 
  signal data_3_FFX_RST : STD_LOGIC; 
  signal address_1_FFX_RST : STD_LOGIC; 
  signal address_2_FFX_RST : STD_LOGIC; 
  signal data_5_FFX_RST : STD_LOGIC; 
  signal data_7_FFX_RST : STD_LOGIC; 
  signal data_1_FFX_RST : STD_LOGIC; 
  signal AD_6_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_6_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_6_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal AD_7_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal AD_7_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal AD_7_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal address_0_FFX_RST : STD_LOGIC; 
  signal Mtrien_AD_FFY_RST : STD_LOGIC; 
  signal address_4_FFY_RST : STD_LOGIC; 
  signal oldmode_1_FFY_RST : STD_LOGIC; 
  signal oldmode_1_FFX_RST : STD_LOGIC; 
  signal address_3_FFX_RST : STD_LOGIC; 
  signal data_0_FFX_RST : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal staterw : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal address : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal data : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal mode : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal oldmode : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Q_n0031 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Q_n0029 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Q_n0190 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal Q_n0229 : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Q_n0189 : STD_LOGIC_VECTOR ( 34 downto 34 ); 
  signal Q_n0035 : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Q_n0040 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mtridata_AD : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  staterw_0_LOGIC_ZERO_0 : X_ZERO
    port map (
      O => staterw_0_LOGIC_ZERO
    );
  staterw_0_LOGIC_ONE_1 : X_ONE
    port map (
      O => staterw_0_LOGIC_ONE
    );
  staterw_0_DXMUX_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N3,
      O => staterw_0_DXMUX
    );
  staterw_0_CYMUXF : X_MUX2
    port map (
      IA => staterw_0_LOGIC_ONE,
      IB => staterw_0_CYINIT,
      SEL => staterw_0_CYSELF,
      O => cancommunication_n0032_0_cyo
    );
  staterw_0_CYINIT_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => staterw_0_CYINIT
    );
  staterw_0_CYSELF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N3,
      O => staterw_0_CYSELF
    );
  staterw_0_DYMUX_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_0_XORG,
      O => staterw_0_DYMUX
    );
  staterw_0_XORG_6 : X_XOR2
    port map (
      I0 => cancommunication_n0032_0_cyo,
      I1 => Q_n0043_1_1_O,
      O => staterw_0_XORG
    );
  staterw_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => staterw_0_CYMUXG,
      O => cancommunication_n0032_1_cyo
    );
  staterw_0_CYMUXG_7 : X_MUX2
    port map (
      IA => staterw_0_LOGIC_ZERO,
      IB => cancommunication_n0032_0_cyo,
      SEL => staterw_0_CYSELG,
      O => staterw_0_CYMUXG
    );
  staterw_0_CYSELG_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0043_1_1_O,
      O => staterw_0_CYSELG
    );
  staterw_0_SRINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => staterw_0_SRINV
    );
  staterw_0_CLKINV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => staterw_0_CLKINV
    );
  staterw_0_CEINV_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0183_0,
      O => staterw_0_CEINV
    );
  Q_n0043_1_1 : X_LUT4
    generic map(
      INIT => X"0054"
    )
    port map (
      ADR0 => Q_n0060,
      ADR1 => N711_0,
      ADR2 => staterw(1),
      ADR3 => Q_n0049_0,
      O => Q_n0043_1_1_O
    );
  staterw_2_LOGIC_ZERO_12 : X_ZERO
    port map (
      O => staterw_2_LOGIC_ZERO
    );
  staterw_2_DXMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (