cancommunication_timesim.vhd

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

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-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: cancommunication_timesim.vhd
-- /___/   /\     Timestamp: Tue Nov 22 15:55:39 2005
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -s 4 -pcf cancommunication.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim cancommunication.ncd cancommunication_timesim.vhd 
-- Device: 3s200ft256-4 (PRODUCTION 1.35 2005-01-22)
-- Design Name: cancommunication
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity cancommunication is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    CS : out STD_LOGIC; 
    RD : out STD_LOGIC; 
    WR : out STD_LOGIC; 
    ALE : out STD_LOGIC; 
    AD : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end cancommunication;

architecture Structure of cancommunication is
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Q_n0183_0 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal Q_n0060 : STD_LOGIC; 
  signal Q_n0065 : STD_LOGIC; 
  signal Q_n0049_0 : STD_LOGIC; 
  signal CHOICE164_0 : STD_LOGIC; 
  signal N711_0 : STD_LOGIC; 
  signal cancommunication_n0032_1_cyo : STD_LOGIC; 
  signal N77_0 : STD_LOGIC; 
  signal N78_0 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal N789_0 : STD_LOGIC; 
  signal N790_0 : STD_LOGIC; 
  signal N65 : STD_LOGIC; 
  signal cancommunication_n0032_3_cyo : STD_LOGIC; 
  signal Q_n0066 : STD_LOGIC; 
  signal N759_0 : STD_LOGIC; 
  signal N761_0 : STD_LOGIC; 
  signal cancommunication_n0032_5_cyo : STD_LOGIC; 
  signal N763_0 : STD_LOGIC; 
  signal N765_0 : STD_LOGIC; 
  signal cancommunication_n0032_7_cyo : STD_LOGIC; 
  signal N767_0 : STD_LOGIC; 
  signal N769_0 : STD_LOGIC; 
  signal cancommunication_n0032_9_cyo : STD_LOGIC; 
  signal N771_0 : STD_LOGIC; 
  signal N773_0 : STD_LOGIC; 
  signal cancommunication_n0032_11_cyo : STD_LOGIC; 
  signal N775_0 : STD_LOGIC; 
  signal N777_0 : STD_LOGIC; 
  signal cancommunication_n0032_13_cyo : STD_LOGIC; 
  signal N779_0 : STD_LOGIC; 
  signal N781_0 : STD_LOGIC; 
  signal cancommunication_n0032_15_cyo : STD_LOGIC; 
  signal N783_0 : STD_LOGIC; 
  signal N785_0 : STD_LOGIC; 
  signal cancommunication_n0032_17_cyo : STD_LOGIC; 
  signal N60_0 : STD_LOGIC; 
  signal N22_0 : STD_LOGIC; 
  signal cancommunication_n0032_19_cyo : STD_LOGIC; 
  signal cancommunication_n0032_21_cyo : STD_LOGIC; 
  signal cancommunication_n0032_23_cyo : STD_LOGIC; 
  signal cancommunication_n0032_25_cyo : STD_LOGIC; 
  signal cancommunication_n0032_27_cyo : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal Q_n0181_0 : STD_LOGIC; 
  signal Mtrien_AD : STD_LOGIC; 
  signal N719 : STD_LOGIC; 
  signal N720 : STD_LOGIC; 
  signal N721 : STD_LOGIC; 
  signal N722 : STD_LOGIC; 
  signal N723 : STD_LOGIC; 
  signal N716 : STD_LOGIC; 
  signal N717 : STD_LOGIC; 
  signal N718 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal N67 : STD_LOGIC; 
  signal Q_n0180_0 : STD_LOGIC; 
  signal state_FFd1 : STD_LOGIC; 
  signal state_FFd4 : STD_LOGIC; 
  signal state_FFd3 : STD_LOGIC; 
  signal state_FFd2 : STD_LOGIC; 
  signal Q_n0187_0 : STD_LOGIC; 
  signal Q_n0190_1_0 : STD_LOGIC; 
  signal N44_0 : STD_LOGIC; 
  signal N47_0 : STD_LOGIC; 
  signal Q_n0175_0 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal CHOICE133_0 : STD_LOGIC; 
  signal CHOICE139 : STD_LOGIC; 
  signal N63 : STD_LOGIC; 
  signal CHOICE15_0 : STD_LOGIC; 
  signal CHOICE21 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal CHOICE110 : STD_LOGIC; 
  signal Q_n0069 : STD_LOGIC; 
  signal CHOICE183 : STD_LOGIC; 
  signal N745_0 : STD_LOGIC; 
  signal N735_0 : STD_LOGIC; 
  signal N751 : STD_LOGIC; 
  signal CHOICE190 : STD_LOGIC; 
  signal CHOICE223 : STD_LOGIC; 
  signal CHOICE62_0 : STD_LOGIC; 
  signal CHOICE69_0 : STD_LOGIC; 
  signal N796_0 : STD_LOGIC; 
  signal N184 : STD_LOGIC; 
  signal N186 : STD_LOGIC; 
  signal N182_0 : STD_LOGIC; 
  signal CHOICE176 : STD_LOGIC; 
  signal Q_n0100 : STD_LOGIC; 
  signal N14_0 : STD_LOGIC; 
  signal Q_n0189_34_0 : STD_LOGIC; 
  signal CHOICE49_0 : STD_LOGIC; 
  signal Ker65_0 : STD_LOGIC; 
  signal N737_0 : STD_LOGIC; 
  signal N753_0 : STD_LOGIC; 
  signal CHOICE123 : STD_LOGIC; 
  signal N755_0 : STD_LOGIC; 
  signal CHOICE144_0 : STD_LOGIC; 
  signal N68_0 : STD_LOGIC; 
  signal mode_1_1 : STD_LOGIC; 
  signal mode_2_1 : STD_LOGIC; 
  signal mode_0_1 : STD_LOGIC; 
  signal N739_0 : STD_LOGIC; 
  signal N62_0 : STD_LOGIC; 
  signal N75_0 : STD_LOGIC; 
  signal N749_0 : STD_LOGIC; 
  signal CHOICE199_0 : STD_LOGIC; 
  signal CHOICE206_0 : STD_LOGIC; 
  signal CHOICE214_0 : STD_LOGIC; 
  signal CHOICE221_0 : STD_LOGIC; 
  signal Q_n0061 : STD_LOGIC; 
  signal Q_n0184_SW0_O : STD_LOGIC; 
  signal N45_0 : STD_LOGIC; 
  signal Q_n0185_SW0_O : STD_LOGIC; 
  signal CHOICE77_0 : STD_LOGIC; 
  signal CHOICE80_0 : STD_LOGIC; 
  signal Q_n014731_O : STD_LOGIC; 
  signal N792_0 : STD_LOGIC; 
  signal N4_0 : STD_LOGIC; 
  signal Q_n0147_0 : STD_LOGIC; 
  signal N802_0 : STD_LOGIC; 
  signal Q_n018141_SW0_O : STD_LOGIC; 
  signal CHOICE147_0 : STD_LOGIC; 
  signal Ker59159_SW2_O : STD_LOGIC; 
  signal N148_0 : STD_LOGIC; 
  signal CHOICE115_0 : STD_LOGIC; 
  signal Q_n018230_SW0_O : STD_LOGIC; 
  signal Q_n0182_0 : STD_LOGIC; 
  signal N5_0 : STD_LOGIC; 
  signal N105_0 : STD_LOGIC; 
  signal N74_0 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N806_0 : STD_LOGIC; 
  signal N102_0 : STD_LOGIC; 
  signal N804 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal CHOICE6 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal staterw_0_DXMUX : STD_LOGIC; 
  signal staterw_0_LOGIC_ONE : STD_LOGIC; 
  signal staterw_0_CYINIT : STD_LOGIC; 
  signal staterw_0_CYSELF : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal staterw_0_DYMUX : STD_LOGIC; 
  signal staterw_0_XORG : STD_LOGIC; 
  signal staterw_0_CYMUXG : STD_LOGIC; 
  signal cancommunication_n0032_0_cyo : STD_LOGIC; 
  signal staterw_0_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_0_CYSELG : STD_LOGIC; 
  signal Q_n0043_1_1_O : STD_LOGIC; 
  signal staterw_0_SRINV : STD_LOGIC; 
  signal staterw_0_CLKINV : STD_LOGIC; 
  signal staterw_0_CEINV : STD_LOGIC; 
  signal staterw_2_DXMUX : STD_LOGIC; 
  signal staterw_2_XORF : STD_LOGIC; 
  signal staterw_2_CYINIT : STD_LOGIC; 
  signal Q_n0043_2_1_O : STD_LOGIC; 
  signal staterw_2_DYMUX : STD_LOGIC; 
  signal staterw_2_XORG : STD_LOGIC; 
  signal cancommunication_n0032_2_cyo : STD_LOGIC; 
  signal staterw_2_CYSELF : STD_LOGIC; 
  signal staterw_2_CYMUXFAST : STD_LOGIC; 
  signal staterw_2_CYAND : STD_LOGIC; 
  signal staterw_2_FASTCARRY : STD_LOGIC; 
  signal staterw_2_CYMUXG2 : STD_LOGIC; 
  signal staterw_2_CYMUXF2 : STD_LOGIC; 
  signal staterw_2_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_2_CYSELG : STD_LOGIC; 
  signal Q_n0043_3_O : STD_LOGIC; 
  signal staterw_2_SRINV : STD_LOGIC; 
  signal staterw_2_CLKINV : STD_LOGIC; 
  signal staterw_2_CEINV : STD_LOGIC; 
  signal staterw_4_DXMUX : STD_LOGIC; 
  signal staterw_4_XORF : STD_LOGIC; 
  signal staterw_4_CYINIT : STD_LOGIC; 
  signal Q_n0043_4_1_O : STD_LOGIC; 
  signal staterw_4_DYMUX : STD_LOGIC; 
  signal staterw_4_XORG : STD_LOGIC; 
  signal cancommunication_n0032_4_cyo : STD_LOGIC; 
  signal staterw_4_CYSELF : STD_LOGIC; 
  signal staterw_4_CYMUXFAST : STD_LOGIC; 
  signal staterw_4_CYAND : STD_LOGIC; 
  signal staterw_4_FASTCARRY : STD_LOGIC; 
  signal staterw_4_CYMUXG2 : STD_LOGIC; 
  signal staterw_4_CYMUXF2 : STD_LOGIC; 
  signal staterw_4_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_4_CYSELG : STD_LOGIC; 
  signal Q_n0043_5_1_O : STD_LOGIC; 
  signal staterw_4_SRINV : STD_LOGIC; 
  signal staterw_4_CLKINV : STD_LOGIC; 
  signal staterw_4_CEINV : STD_LOGIC; 
  signal staterw_6_DXMUX : STD_LOGIC; 
  signal staterw_6_XORF : STD_LOGIC; 
  signal staterw_6_CYINIT : STD_LOGIC; 
  signal Q_n0043_6_1_O : STD_LOGIC; 
  signal staterw_6_DYMUX : STD_LOGIC; 
  signal staterw_6_XORG : STD_LOGIC; 
  signal cancommunication_n0032_6_cyo : STD_LOGIC; 
  signal staterw_6_CYSELF : STD_LOGIC; 
  signal staterw_6_CYMUXFAST : STD_LOGIC; 
  signal staterw_6_CYAND : STD_LOGIC; 
  signal staterw_6_FASTCARRY : STD_LOGIC; 
  signal staterw_6_CYMUXG2 : STD_LOGIC; 
  signal staterw_6_CYMUXF2 : STD_LOGIC; 
  signal staterw_6_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_6_CYSELG : STD_LOGIC; 
  signal Q_n0043_7_1_O : STD_LOGIC; 
  signal staterw_6_SRINV : STD_LOGIC; 
  signal staterw_6_CLKINV : STD_LOGIC; 
  signal staterw_6_CEINV : STD_LOGIC; 
  signal staterw_8_DXMUX : STD_LOGIC; 
  signal staterw_8_XORF : STD_LOGIC; 
  signal staterw_8_CYINIT : STD_LOGIC; 
  signal Q_n0043_8_1_O : STD_LOGIC; 
  signal staterw_8_DYMUX : STD_LOGIC; 
  signal staterw_8_XORG : STD_LOGIC; 
  signal cancommunication_n0032_8_cyo : STD_LOGIC; 
  signal staterw_8_CYSELF : STD_LOGIC; 
  signal staterw_8_CYMUXFAST : STD_LOGIC; 
  signal staterw_8_CYAND : STD_LOGIC; 
  signal staterw_8_FASTCARRY : STD_LOGIC; 
  signal staterw_8_CYMUXG2 : STD_LOGIC; 
  signal staterw_8_CYMUXF2 : STD_LOGIC; 
  signal staterw_8_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_8_CYSELG : STD_LOGIC; 
  signal Q_n0043_9_1_O : STD_LOGIC; 
  signal staterw_8_SRINV : STD_LOGIC; 
  signal staterw_8_CLKINV : STD_LOGIC; 
  signal staterw_8_CEINV : STD_LOGIC; 
  signal staterw_10_DXMUX : STD_LOGIC; 
  signal staterw_10_XORF : STD_LOGIC; 
  signal staterw_10_CYINIT : STD_LOGIC; 
  signal Q_n0043_10_1_O : STD_LOGIC; 
  signal staterw_10_DYMUX : STD_LOGIC; 
  signal staterw_10_XORG : STD_LOGIC; 
  signal cancommunication_n0032_10_cyo : STD_LOGIC; 
  signal staterw_10_CYSELF : STD_LOGIC; 
  signal staterw_10_CYMUXFAST : STD_LOGIC; 
  signal staterw_10_CYAND : STD_LOGIC; 
  signal staterw_10_FASTCARRY : STD_LOGIC; 
  signal staterw_10_CYMUXG2 : STD_LOGIC; 
  signal staterw_10_CYMUXF2 : STD_LOGIC; 
  signal staterw_10_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_10_CYSELG : STD_LOGIC; 
  signal Q_n0043_11_1_O : STD_LOGIC; 
  signal staterw_10_SRINV : STD_LOGIC; 
  signal staterw_10_CLKINV : STD_LOGIC; 
  signal staterw_10_CEINV : STD_LOGIC; 
  signal staterw_12_DXMUX : STD_LOGIC; 
  signal staterw_12_XORF : STD_LOGIC; 
  signal staterw_12_CYINIT : STD_LOGIC; 
  signal Q_n0043_12_1_O : STD_LOGIC; 
  signal staterw_12_DYMUX : STD_LOGIC; 
  signal staterw_12_XORG : STD_LOGIC; 
  signal cancommunication_n0032_12_cyo : STD_LOGIC; 
  signal staterw_12_CYSELF : STD_LOGIC; 
  signal staterw_12_CYMUXFAST : STD_LOGIC; 
  signal staterw_12_CYAND : STD_LOGIC; 
  signal staterw_12_FASTCARRY : STD_LOGIC; 
  signal staterw_12_CYMUXG2 : STD_LOGIC; 
  signal staterw_12_CYMUXF2 : STD_LOGIC; 
  signal staterw_12_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_12_CYSELG : STD_LOGIC; 
  signal Q_n0043_13_1_O : STD_LOGIC; 
  signal staterw_12_SRINV : STD_LOGIC; 
  signal staterw_12_CLKINV : STD_LOGIC; 
  signal staterw_12_CEINV : STD_LOGIC; 
  signal staterw_14_DXMUX : STD_LOGIC; 
  signal staterw_14_XORF : STD_LOGIC; 
  signal staterw_14_CYINIT : STD_LOGIC; 
  signal Q_n0043_14_1_O : STD_LOGIC; 
  signal staterw_14_DYMUX : STD_LOGIC; 
  signal staterw_14_XORG : STD_LOGIC; 
  signal cancommunication_n0032_14_cyo : STD_LOGIC; 
  signal staterw_14_CYSELF : STD_LOGIC; 
  signal staterw_14_CYMUXFAST : STD_LOGIC; 
  signal staterw_14_CYAND : STD_LOGIC; 
  signal staterw_14_FASTCARRY : STD_LOGIC; 
  signal staterw_14_CYMUXG2 : STD_LOGIC; 
  signal staterw_14_CYMUXF2 : STD_LOGIC; 
  signal staterw_14_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_14_CYSELG : STD_LOGIC; 
  signal Q_n0043_15_1_O : STD_LOGIC; 
  signal staterw_14_SRINV : STD_LOGIC; 
  signal staterw_14_CLKINV : STD_LOGIC; 
  signal staterw_14_CEINV : STD_LOGIC; 
  signal N783 : STD_LOGIC; 
  signal N65_pack_1 : STD_LOGIC; 
  signal N735 : STD_LOGIC; 
  signal CHOICE176_pack_1 : STD_LOGIC; 
  signal Q_n0180 : STD_LOGIC; 
  signal Q_n0100_pack_1 : STD_LOGIC; 
  signal N761 : STD_LOGIC; 
  signal N184_pack_1 : STD_LOGIC; 
  signal CHOICE144 : STD_LOGIC; 
  signal Q_n0065_pack_1 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N67_pack_1 : STD_LOGIC; 
  signal Ker65 : STD_LOGIC; 
  signal Q_n0069_pack_1 : STD_LOGIC; 
  signal N739 : STD_LOGIC; 
  signal CHOICE110_pack_1 : STD_LOGIC; 
  signal N75 : STD_LOGIC; 
  signal Q_n0060_pack_1 : STD_LOGIC; 
  signal N790 : STD_LOGIC; 
  signal Q_n0066_pack_1 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal CHOICE223_pack_1 : STD_LOGIC; 
  signal N759 : STD_LOGIC; 
  signal N186_pack_1 : STD_LOGIC; 
  signal CHOICE164 : STD_LOGIC; 
  signal Q_n0061_pack_1 : STD_LOGIC; 
  signal N753 : STD_LOGIC; 
  signal CHOICE190_pack_1 : STD_LOGIC; 
  signal Q_n0184 : STD_LOGIC; 
  signal Q_n0184_SW0_O_pack_1 : STD_LOGIC; 
  signal Q_n0185 : STD_LOGIC; 
  signal Q_n0185_SW0_O_pack_1 : STD_LOGIC; 
  signal Q_n0147 : STD_LOGIC; 
  signal Q_n014731_O_pack_1 : STD_LOGIC; 
  signal N60 : STD_LOGIC; 
  signal N80_pack_1 : STD_LOGIC; 
  signal Q_n0181 : STD_LOGIC; 
  signal Q_n018141_SW0_O_pack_1 : STD_LOGIC; 
  signal N711 : STD_LOGIC; 
  signal Ker59159_SW2_O_pack_1 : STD_LOGIC; 
  signal Q_n0182 : STD_LOGIC; 
  signal Q_n018230_SW0_O_pack_1 : STD_LOGIC; 
  signal Q_n0034 : STD_LOGIC; 
  signal Mtrien_AD_DYMUX : STD_LOGIC; 
  signal Q_n0041 : STD_LOGIC; 
  signal Mtrien_AD_CLKINV : STD_LOGIC; 
  signal Mtrien_AD_CEINV : STD_LOGIC; 
  signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal address_0_DXMUX : STD_LOGIC; 
  signal address_0_F5MUX : STD_LOGIC; 
  signal N819 : STD_LOGIC; 
  signal address_0_BXINV : STD_LOGIC; 
  signal N818 : STD_LOGIC; 
  signal address_0_CLKINV : STD_LOGIC; 
  signal address_0_CEINV : STD_LOGIC; 
  signal address_1_DXMUX : STD_LOGIC; 
  signal address_1_F5MUX : STD_LOGIC; 
  signal N809 : STD_LOGIC; 
  signal address_1_BXINV : STD_LOGIC; 
  signal N808 : STD_LOGIC; 
  signal address_1_CLKINV : STD_LOGIC; 
  signal address_1_CEINV : STD_LOGIC; 
  signal address_2_DXMUX : STD_LOGIC; 
  signal address_2_F5MUX : STD_LOGIC; 
  signal N823 : STD_LOGIC; 
  signal address_2_BXINV : STD_LOGIC; 
  signal N822 : STD_LOGIC; 
  signal address_2_CLKINV : STD_LOGIC; 
  signal address_2_CEINV : STD_LOGIC; 
  signal data_5_DXMUX : STD_LOGIC; 
  signal data_5_F5MUX : STD_LOGIC; 
  signal N827 : STD_LOGIC; 
  signal data_5_BXINV : STD_LOGIC; 
  signal N826 : STD_LOGIC; 
  signal data_5_CLKINV : STD_LOGIC; 
  signal data_5_CEINV : STD_LOGIC; 
  signal data_7_DXMUX : STD_LOGIC; 
  signal data_7_F5MUX : STD_LOGIC; 
  signal N813 : STD_LOGIC; 
  signal data_7_BXINV : STD_LOGIC; 
  signal N812 : STD_LOGIC; 
  signal data_7_CLKINV : STD_LOGIC; 
  signal data_7_CEINV : STD_LOGIC; 
  signal CHOICE139_F5MUX : STD_LOGIC; 
  signal Q_n018757_G_O : STD_LOGIC; 
  signal CHOICE139_BXINV : STD_LOGIC; 
  signal Q_n018757_F_O : STD_LOGIC; 
  signal data_1_DXMUX : STD_LOGIC; 
  signal data_1_F5MUX : STD_LOGIC; 
  signal N817 : STD_LOGIC; 
  signal data_1_BXINV : STD_LOGIC; 
  signal N816 : STD_LOGIC; 
  signal data_1_CLKINV : STD_LOGIC; 
  signal data_1_CEINV : STD_LOGIC; 
  signal CHOICE21_F5MUX : STD_LOGIC; 
  signal N831 : STD_LOGIC; 
  signal CHOICE21_BXINV : STD_LOGIC; 
  signal N830 : STD_LOGIC; 
  signal data_2_DXMUX : STD_LOGIC; 
  signal data_2_F5MUX : STD_LOGIC; 
  signal N815 : STD_LOGIC; 
  signal data_2_BXINV : STD_LOGIC; 
  signal N814 : STD_LOGIC; 
  signal data_2_CLKINV : STD_LOGIC; 
  signal data_2_CEINV : STD_LOGIC; 
  signal data_4_DXMUX : STD_LOGIC; 
  signal data_4_F5MUX : STD_LOGIC; 
  signal N829 : STD_LOGIC; 
  signal data_4_BXINV : STD_LOGIC; 
  signal N828 : STD_LOGIC; 
  signal data_4_CLKINV : STD_LOGIC; 
  signal data_4_CEINV : STD_LOGIC; 
  signal data_6_DXMUX : STD_LOGIC; 
  signal data_6_F5MUX : STD_LOGIC; 
  signal N821 : STD_LOGIC; 
  signal data_6_BXINV : STD_LOGIC; 
  signal N820 : STD_LOGIC; 
  signal data_6_CLKINV : STD_LOGIC; 
  signal data_6_CEINV : STD_LOGIC; 
  signal data_3_DXMUX : STD_LOGIC; 
  signal data_3_F5MUX : STD_LOGIC; 
  signal N825 : STD_LOGIC; 
  signal data_3_BXINV : STD_LOGIC; 
  signal N824 : STD_LOGIC; 
  signal data_3_CLKINV : STD_LOGIC; 
  signal data_3_CEINV : STD_LOGIC; 
  signal Q_n0030_6_1_O : STD_LOGIC; 
  signal N61_pack_1 : STD_LOGIC; 
  signal N745 : STD_LOGIC; 
  signal CHOICE183_pack_1 : STD_LOGIC; 
  signal Q_n0049 : STD_LOGIC; 
  signal N751_pack_1 : STD_LOGIC; 
  signal N796 : STD_LOGIC; 
  signal N8_pack_1 : STD_LOGIC; 
  signal staterw_30_DXMUX : STD_LOGIC; 
  signal staterw_30_XORF : STD_LOGIC; 
  signal staterw_30_LOGIC_ZERO : STD_LOGIC; 
  signal staterw_30_CYINIT : STD_LOGIC; 
  signal staterw_30_CYSELF : STD_LOGIC; 
  signal Q_n0043_30_1_O : STD_LOGIC; 
  signal staterw_30_DYMUX : STD_LOGIC; 
  signal staterw_30_XORG : STD_LOGIC; 
  signal cancommunication_n0032_30_cyo : STD_LOGIC; 
  signal Q_n0043_31_1_O : STD_LOGIC; 
  signal staterw_30_SRINV : STD_LOGIC; 
  signal staterw_30_CLKINV : STD_LOGIC; 
  signal staterw_30_CEINV : STD_LOGIC; 
  signal clk_INBUF : STD_LOGIC; 
  signal CS_ENABLE : STD_LOGIC; 
  signal CS_O : STD_LOGIC; 
  signal WR_ENABLE : STD_LOGIC; 
  signal WR_O : STD_LOGIC; 
  signal WR_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal WR_OBUF : STD_LOGIC; 
  signal WR_OUTPUT_OFF_OCEINV : STD_LOGIC;