cancommunication.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Register <mode_12> equivalent to <mode_3> has been removed
Register <mode_11> equivalent to <mode_3> has been removed
Register <mode_10> equivalent to <mode_3> has been removed
Register <mode_9> equivalent to <mode_3> has been removed
Register <mode_8> equivalent to <mode_3> has been removed
Register <mode_7> equivalent to <mode_3> has been removed
Register <mode_6> equivalent to <mode_3> has been removed
Register <mode_5> equivalent to <mode_3> has been removed
Register <mode_4> equivalent to <mode_3> has been removed
Register <mode_27> equivalent to <mode_3> has been removed
Register <mode_29> equivalent to <mode_3> has been removed
Register <mode_28> equivalent to <mode_3> has been removed
WARNING:Xst:1988 - Unit <cancommunication>: instances <Mcompar__n0063>, <Mcompar__n0041> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1293 - FF/Latch  <mode_3> has a constant value of 0 in block <cancommunication>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <address_5> has a constant value of 0 in block <cancommunication>.

Optimizing unit <cancommunication> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cancommunication, actual ratio is 10.
FlipFlop mode_0 has been replicated 2 time(s)
FlipFlop mode_1 has been replicated 2 time(s)
FlipFlop mode_2 has been replicated 3 time(s)
FlipFlop staterw_1 has been replicated 2 time(s)
FlipFlop staterw_2 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cancommunication.ngr
Top Level Output File Name         : cancommunication
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 22

Macro Statistics :
# Registers                        : 13
#      1-bit register              : 5
#      2-bit register              : 1
#      32-bit register             : 3
#      8-bit register              : 4
# Counters                         : 1
#      32-bit down counter         : 1
# Multiplexers                     : 4
#      1-bit 4-to-1 multiplexer    : 2
#      8-bit 4-to-1 multiplexer    : 2
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 4
#      32-bit adder                : 3
#      32-bit subtractor           : 1
# Comparators                      : 2
#      32-bit comparator greatequal: 1
#      32-bit comparator less      : 1

Cell Usage :
# BELS                             : 741
#      GND                         : 1
#      INV                         : 34
#      LUT1                        : 32
#      LUT1_L                      : 34
#      LUT2                        : 22
#      LUT2_D                      : 4
#      LUT2_L                      : 34
#      LUT3                        : 54
#      LUT3_D                      : 5
#      LUT3_L                      : 11
#      LUT4                        : 110
#      LUT4_D                      : 15
#      LUT4_L                      : 54
#      MUXCY                       : 166
#      MUXF5                       : 11
#      VCC                         : 1
#      XORCY                       : 153
# FlipFlops/Latches                : 151
#      FDE                         : 115
#      FDR                         : 32
#      FDRE                        : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 21
#      IBUF                        : 1
#      IOBUF                       : 8
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     229  out of   1920    11%  
 Number of Slice Flip Flops:           151  out of   3840     3%  
 Number of 4 input LUTs:               375  out of   3840     9%  
 Number of bonded IOBs:                 22  out of    173    12%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 151   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 15.152ns (Maximum Frequency: 65.996MHz)
   Minimum input arrival time before clock: 8.065ns
   Maximum output required time after clock: 7.690ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 15.152ns (frequency: 65.996MHz)
  Total number of paths / destination ports: 224430 / 302
-------------------------------------------------------------------------
Delay:               15.152ns (Levels of Logic = 34)
  Source:            staterw_15 (FF)
  Destination:       staterw_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: staterw_15 to staterw_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.720   1.216  staterw_15 (staterw_15)
     LUT4:I0->O            2   0.551   0.903  Ker6792 (CHOICE278)
     LUT4:I3->O           18   0.551   1.443  Ker6796 (CHOICE279)
     LUT4_D:I3->O          7   0.551   1.134  Ker911 (N911)
     LUT3_D:I2->O         27   0.551   2.163  _n00561 (_n0211<1>)
     LUT4_L:I0->LO         1   0.551   0.000  _n0051<4>1 (_n0051<4>)
     MUXCY:S->O            1   0.500   0.000  cancommunication__n0053<4>cy (cancommunication__n0053<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<5>cy (cancommunication__n0053<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<6>cy (cancommunication__n0053<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<7>cy (cancommunication__n0053<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<8>cy (cancommunication__n0053<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<9>cy (cancommunication__n0053<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<10>cy (cancommunication__n0053<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<11>cy (cancommunication__n0053<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<12>cy (cancommunication__n0053<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<13>cy (cancommunication__n0053<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<14>cy (cancommunication__n0053<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<15>cy (cancommunication__n0053<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<16>cy (cancommunication__n0053<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<17>cy (cancommunication__n0053<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<18>cy (cancommunication__n0053<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<19>cy (cancommunication__n0053<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<20>cy (cancommunication__n0053<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<21>cy (cancommunication__n0053<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<22>cy (cancommunication__n0053<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<23>cy (cancommunication__n0053<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<24>cy (cancommunication__n0053<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<25>cy (cancommunication__n0053<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<26>cy (cancommunication__n0053<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<27>cy (cancommunication__n0053<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<28>cy (cancommunication__n0053<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  cancommunication__n0053<29>cy (cancommunication__n0053<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  cancommunication__n0053<30>cy (cancommunication__n0053<30>_cyo)
     XORCY:CI->O           1   0.904   0.996  cancommunication__n0053<31>_xor (_n0053<31>)
     LUT2_L:I1->LO         1   0.551   0.000  _n0035<31>1 (_n0035<31>)
     FDE:D                     0.203          staterw_31
    ----------------------------------------
    Total                     15.152ns (7.297ns logic, 7.855ns route)
                                       (48.2% logic, 51.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 750 / 218
-------------------------------------------------------------------------
Offset:              8.065ns (Levels of Logic = 3)
  Source:            reset (PAD)
  Destination:       staterw_10 (FF)
  Destination Clock: clk rising

  Data Path: reset to staterw_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            89   0.821   2.519  reset_IBUF (reset_IBUF)
     LUT4:I0->O            1   0.551   1.140  _n02011 (N62)
     LUT2:I0->O           37   0.551   1.882  _n02012 (_n0201)
     FDE:CE                    0.602          staterw_0
    ----------------------------------------
    Total                      8.065ns (2.525ns logic, 5.540ns route)
                                       (31.3% logic, 68.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 28 / 20
-------------------------------------------------------------------------
Offset:              7.690ns (Levels of Logic = 1)
  Source:            Mtrien_AD (FF)
  Destination:       AD<5> (PAD)
  Source Clock:      clk rising

  Data Path: Mtrien_AD to AD<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              8   0.720   1.083  Mtrien_AD (Mtrien_AD)
     IOBUF:T->IO               5.887          AD_7_IOBUF (AD<7>)
    ----------------------------------------
    Total                      7.690ns (6.607ns logic, 1.083ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 22.52 / 22.96 s | Elapsed : 22.00 / 22.00 s
 
--> 

Total memory usage is 100180 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    1 (   0 filtered)