cancommunication.syr

此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: cancommunication.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "cancommunication.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "cancommunication"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : cancommunication
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : cancommunication.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "Z:/work/speedmes/can2.vhd" in Library work.
Entity <cancommunication> compiled.
Entity <cancommunication> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cancommunication> (Architecture <behavioral>).
Entity <cancommunication> analyzed. Unit <cancommunication> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cancommunication>.
    Related source file is "Z:/work/speedmes/can2.vhd".
WARNING:Xst:1778 - Inout <STATUS> is assigned but never used.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 15                                             |
    | Inputs             | 1                                              |
    | Outputs            | 43                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0007 (positive)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000000000000000000000000000000               |
    | Power Up State     | 00000000000000000000000000000000               |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <AD>.
    Found 8-bit register for signal <STATUS>.
    Found 1-bit register for signal <ALE>.
    Found 1-bit register for signal <RD>.
    Found 1-bit register for signal <WR>.
    Found 1-bit register for signal <CS>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0031>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0034>.
    Found 32-bit comparator greatequal for signal <$n0041> created at line 59.
    Found 8-bit 4-to-1 multiplexer for signal <$n0046>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0048> created at line 145.
    Found 32-bit adder for signal <$n0049> created at line 58.
    Found 32-bit subtractor for signal <$n0052> created at line 73.
    Found 32-bit adder for signal <$n0053>.
    Found 32-bit comparator less for signal <$n0063> created at line 59.
    Found 8-bit register for signal <address>.
    Found 8-bit register for signal <data>.
    Found 32-bit register for signal <mode>.
    Found 8-bit register for signal <Mtridata_AD> created at line 149.
    Found 1-bit register for signal <Mtrien_AD> created at line 149.
    Found 2-bit register for signal <oldmode>.
    Found 32-bit up counter for signal <scaler>.
    Found 32-bit register for signal <staterw>.
    Found 32-bit down counter for signal <warten>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 103 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  18 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <cancommunication> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:4]> with sequential encoding.
----------------------------------------------
 State                            | Encoding
----------------------------------------------
 00000000000000000000000000000000 | 0000
 00000000000000000000000000000001 | 0001
 00000000000000000000000000000010 | 0010
 00000000000000000000000000000011 | 0011
 00000000000000000000000000000100 | 0100
 00000000000000000000000000000101 | 0101
 00000000000000000000000000000110 | 0110
 00000000000000000000000000000111 | 0111
 00000000000000000000000000001000 | 1000
 00000000000000000000000000001001 | 1001
 00000000000000000000000000001010 | 1010
 00000000000000000000000000001011 | 1011
----------------------------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 3
 32-bit adder                      : 2
 32-bit subtractor                 : 1
# Counters                         : 2
 32-bit down counter               : 1
 32-bit up counter                 : 1
# Registers                        : 16
 1-bit register                    : 9
 2-bit register                    : 1
 32-bit register                   : 2
 8-bit register                    : 4
# Comparators                      : 2
 32-bit comparator greatequal      : 1
 32-bit comparator less            : 1
# Multiplexers                     : 4
 1-bit 4-to-1 multiplexer          : 2
 8-bit 4-to-1 multiplexer          : 2
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Register <address_7> equivalent to <address_5> has been removed
Register <address_6> equivalent to <address_5> has been removed
Register <mode_31> equivalent to <mode_3> has been removed
Register <mode_30> equivalent to <mode_3> has been removed
Register <mode_26> equivalent to <mode_3> has been removed
Register <mode_25> equivalent to <mode_3> has been removed
Register <mode_24> equivalent to <mode_3> has been removed
Register <mode_23> equivalent to <mode_3> has been removed
Register <mode_22> equivalent to <mode_3> has been removed
Register <mode_21> equivalent to <mode_3> has been removed
Register <mode_20> equivalent to <mode_3> has been removed
Register <mode_19> equivalent to <mode_3> has been removed
Register <mode_18> equivalent to <mode_3> has been removed
Register <mode_17> equivalent to <mode_3> has been removed
Register <mode_16> equivalent to <mode_3> has been removed
Register <mode_15> equivalent to <mode_3> has been removed
Register <mode_14> equivalent to <mode_3> has been removed
Register <mode_13> equivalent to <mode_3> has been removed