wallce_tree_tp.v.bak

fpga功能实现有限字长响应FIR 用verilog编写

`timescale 1ns/1ns
module wallce_tree_tp();
reg[2:0] i;
reg[8:0] x;
wire[7:0] h;
wire[16:0] out;
wallce_tree tree_1(i,x,h,out);
initial 
   begin
     i=0;x=9'b010101001;
     #10 i=1;x=9'b010101001;
     #10 i=2;x=9'b101010001;
     #10 i=3;x=9'b000101101;
     #10 i=4;x=9'b101010001;
     #10 i=5;x=9'b010101101;
     #10 i=6;x=9'b010101001;
     #10 i=7; x=9'b001010100;
     #10 i=0; x=9'b010001111; 
          #10 i=1;x=9'b010101001;
          #10 i=2;x=9'b010010001;
          #10 i=3;x=9'b010101001;
          #10 i=4;x=9'b010101001;
          #10 i=5;x=9'b010101001;
          #10 i=6;x=9'b010101001;
          #10 i=7;x=9'b010100101; 
   end
endmodule