mux_x.v

来自「fpga功能实现有限字长响应FIR 用verilog编写」· Verilog 代码 · 共 36 行

module mux_x(i,x_i,x_Ni,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15);
input[2:0] i;
input[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15;
output[7:0] x_i,x_Ni;
reg[7:0] x_i,x_Ni;
always @(i)
 begin
     case(i)
     0: begin
         x_i<=x0;x_Ni<=x15;
        end   
     1: begin
          x_i<=x1;x_Ni<=x14;
         end
     2: begin
          x_i<=x2;x_Ni<=x13;
        end
     3: begin
           x_i<=x3;x_Ni<=x12;
            end   
     4: begin
              x_i<=x4;x_Ni<=x11;
             end
     5: begin
              x_i<=x5;x_Ni<=x10;
            end
     6: begin
              x_i<=x6;x_Ni<=x9;
         end   
      7: begin
              x_i<=x7;x_Ni<=x8;
          end
      endcase
 end
endmodule