full_add1_tp.v.bak

来自「fpga功能实现有限字长响应FIR 用verilog编写」· BAK 代码 · 共 18 行

`timescale 1ns/1ns
module full_add1_tp();
reg a,b,cin;
wire sum,cout;
initial 
 begin
      a=0;b=0;cin=0;
#10   a=0;b=0;cin=1;
#10   a=0;b=1;cin=0;
#10   a=0;b=1;cin=1;
#10   a=1;b=0;cin=0;
#10   a=1;b=0;cin=1;
#10   a=1;b=1;cin=0;
#10   a=1;b=1;cin=1;
#10  $stop;
end
endmodule