dff.v.bak

来自「fpga功能实现有限字长响应FIR 用verilog编写」· BAK 代码 · 共 15 行

module Dff(clk,reset,D,Q);
input clk,reset;
input[18:0] D;
output[18:0] Q;
reg[18:0] Q;
reg temp;
always @(posedge reset)
    temp<=1;
always @(posedge clk)
  begin 
     if(temp) begin Q<=0;temp<=0;end
     else Q<=D;
 end
 endmodule