add_12b.v

fpga功能实现有限字长响应FIR 用verilog编写

module add_12b(a,b,out,co);
input[11:0] a,b;
output[12:0] out;
output co;
wire c3,c7,c7_0,c7_1,c11_0,c11_1;
wire[3:0] out0,out1;
wire co,co1;
add_8b add8(a[7:0],b[7:0],0,out[7:0],co1);
CSA4 add4_3(a[11:8],b[11:8],0,out0,c11_0);
CSA4 add4_4(a[11:8],b[11:8],1,out1,c11_1);
assign out[11:8]=(co1==0)?out0:out1;
assign co=(co1==0)?c11_0:c11_1;
assign out[12]=co^a[11]^b[11];
endmodule