booth_code_tp.v.bak

来自「fpga功能实现有限字长响应FIR 用verilog编写」· BAK 代码 · 共 23 行

`timescale 1ns/1ns
module booth_code_tp();
reg[2:0] b;
reg[8:0] x;
wire[9:0] out; 
wire[8:0] temp;
wire co;
booth_code  inst_cnt(b,x,out,temp,co);
initial 
 begin
      b=3'b000;x=9'b100010101;
#10   b=3'b001;x=9'b101010101;
#10   b=3'b010;x=9'b100010101;
#10   b=3'b111;x=9'b100100101;
#10   b=3'b110;x=9'b010100101;
#10   b=3'b000;x=9'b001010101;
#10   b=3'b001;x=9'b100010101;
#10   b=3'b010;x=9'b100010101;
#10   b=3'b111;x=9'b010110101;
#10   b=3'b110;x=9'b000101010;
#10  $stop;
end
endmodule