_primary.vhd

来自「fpga功能实现有限字长响应FIR 用verilog编写」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity booth is
    port(
        h               : in     vl_logic_vector(7 downto 0);
        b0              : out    vl_logic_vector(2 downto 0);
        b1              : out    vl_logic_vector(2 downto 0);
        b2              : out    vl_logic_vector(2 downto 0);
        b3              : out    vl_logic_vector(2 downto 0)
    );
end booth;