wallce_tree_tp.v

来自「fpga功能实现有限字长响应FIR 用verilog编写」· Verilog 代码 · 共 20 行

`timescale 1ns/1ns
module wallce_tree_tp();
reg[8:0] x;
reg[7:0] h;
wire[16:0] out;
wallce_tree tree_1(x,h,out);
initial 
   begin
         x=9'b010101001;h=8'b00000000;
     #10 x=9'b010101001;h=8'b00010000;
     #10 x=9'b101010001;h=8'b11100001;
     #10 x=9'b000101101;h=8'b10010101;
     #10 x=9'b101010001;h=8'b10101001;
     #10 x=9'b010101101;h=8'b10100011;
     #10 x=9'b010101001;h=8'b00101000;
     #10 x=9'b001010100;h=8'b00101011;
     #10 x=9'b010001111;h=8'b10001000;
#10 $stop;
   end
endmodule