add_8b.v.bak

fpga功能实现有限字长响应FIR 用verilog编写

module add_8b(a,b,out,co);
input[7:0] a,b;
output[8:0] out;
output co;
wire c3,c7,c7_0,c7_1;
wire[3:0] out0,out1;
wire t3;
CSA4 add4_0(a[3:0],b[3:0],0,out[3:0],c3);
CSA4 add4_1(a[7:4],b[7:4],0,out0,c7_0);
CSA4 add4_2(a[7:4],b[7:4],1,out1,c7_1);
assign co=(c3==0)?c7_0:c7_1;
assign out[7:4]=(c3==0)?out0:out1;
full_add1 add1(a[7],b[7],co,out[8],t3);

endmodule