shift.tan.rpt

移位寄存器,异步清零,异步置数,左移右移可控,具有循环移位功能

; N/A   ; None         ; 8.626 ns   ; temp[3]~973 ; q3 ; cp         ;
; N/A   ; None         ; 8.625 ns   ; temp[1]~977 ; q1 ; cp         ;
; N/A   ; None         ; 8.305 ns   ; temp[0]~979 ; q0 ; cp         ;
+-------+--------------+------------+-------------+----+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 12.742 ns       ; c    ; q2 ;
; N/A   ; None              ; 12.706 ns       ; CT   ; q2 ;
; N/A   ; None              ; 12.443 ns       ; c    ; q3 ;
; N/A   ; None              ; 12.435 ns       ; c    ; q1 ;
; N/A   ; None              ; 12.409 ns       ; CT   ; q1 ;
; N/A   ; None              ; 12.407 ns       ; CT   ; q3 ;
; N/A   ; None              ; 12.114 ns       ; c    ; q0 ;
; N/A   ; None              ; 12.083 ns       ; CT   ; q0 ;
+-------+-------------------+-----------------+------+----+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -3.914 ns ; x    ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -4.026 ns ; D    ; temp[0]~979 ; cp       ;
; N/A           ; None        ; -4.316 ns ; k    ; temp[1]~977 ; cp       ;
; N/A           ; None        ; -4.501 ns ; x    ; temp[1]~977 ; cp       ;
; N/A           ; None        ; -4.557 ns ; en   ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -4.557 ns ; en   ; temp[0]~979 ; cp       ;
; N/A           ; None        ; -4.557 ns ; en   ; temp[2]~975 ; cp       ;
; N/A           ; None        ; -4.557 ns ; en   ; temp[1]~977 ; cp       ;
; N/A           ; None        ; -4.790 ns ; k    ; temp[0]~979 ; cp       ;
; N/A           ; None        ; -4.791 ns ; k    ; temp[2]~975 ; cp       ;
; N/A           ; None        ; -4.975 ns ; x    ; temp[0]~979 ; cp       ;
; N/A           ; None        ; -4.976 ns ; x    ; temp[2]~975 ; cp       ;
; N/A           ; None        ; -5.118 ns ; CT   ; temp[2]~975 ; cp       ;
; N/A           ; None        ; -5.122 ns ; CT   ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -5.153 ns ; c    ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -5.154 ns ; c    ; temp[2]~975 ; cp       ;
; N/A           ; None        ; -5.206 ns ; k    ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -5.295 ns ; CT   ; temp[1]~977 ; cp       ;
; N/A           ; None        ; -5.331 ns ; c    ; temp[1]~977 ; cp       ;
; N/A           ; None        ; -5.448 ns ; D    ; temp[3]~973 ; cp       ;
; N/A           ; None        ; -5.549 ns ; CT   ; temp[0]~979 ; cp       ;
; N/A           ; None        ; -5.575 ns ; c    ; temp[0]~979 ; cp       ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Nov 28 16:04:34 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shift -c shift --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "temp[3]~224" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" has Internal fmax of 358.81 MHz between source register "temp[2]~975" and destination register "temp[3]~973" (period= 2.787 ns)
    Info: + Longest register to register delay is 2.523 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N13; Fanout = 1; REG Node = 'temp[2]~975'
        Info: 2: + IC(0.446 ns) + CELL(0.206 ns) = 0.652 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 3; COMB Node = 'temp[2]~976'
        Info: 3: + IC(0.393 ns) + CELL(0.370 ns) = 1.415 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'temp[3]~981'
        Info: 4: + IC(0.376 ns) + CELL(0.624 ns) = 2.415 ns; Loc. = LCCOMB_X2_Y1_N30; Fanout = 1; COMB Node = 'temp[3]~982'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.523 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
        Info: Total cell delay = 1.308 ns ( 51.84 % )
        Info: Total interconnect delay = 1.215 ns ( 48.16 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "cp" to destination register is 2.924 ns
            Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
            Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
            Info: Total cell delay = 1.600 ns ( 54.72 % )
            Info: Total interconnect delay = 1.324 ns ( 45.28 % )
        Info: - Longest clock path from clock "cp" to source register is 2.924 ns
            Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
            Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N13; Fanout = 1; REG Node = 'temp[2]~975'
            Info: Total cell delay = 1.600 ns ( 54.72 % )
            Info: Total interconnect delay = 1.324 ns ( 45.28 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "temp[3]~973" (data pin = "c", clock pin = "cp") is 6.598 ns
    Info: + Longest pin to register delay is 9.562 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_25; Fanout = 6; PIN Node = 'c'
        Info: 2: + IC(6.105 ns) + CELL(0.651 ns) = 7.691 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 3; COMB Node = 'temp[2]~976'
        Info: 3: + IC(0.393 ns) + CELL(0.370 ns) = 8.454 ns; Loc. = LCCOMB_X2_Y1_N26; Fanout = 1; COMB Node = 'temp[3]~981'
        Info: 4: + IC(0.376 ns) + CELL(0.624 ns) = 9.454 ns; Loc. = LCCOMB_X2_Y1_N30; Fanout = 1; COMB Node = 'temp[3]~982'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 9.562 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
        Info: Total cell delay = 2.688 ns ( 28.11 % )
        Info: Total interconnect delay = 6.874 ns ( 71.89 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.924 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
        Info: Total cell delay = 1.600 ns ( 54.72 % )
        Info: Total interconnect delay = 1.324 ns ( 45.28 % )
Info: tco from clock "cp" to destination pin "q2" through register "temp[2]~975" is 8.931 ns
    Info: + Longest clock path from clock "cp" to source register is 2.924 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N13; Fanout = 1; REG Node = 'temp[2]~975'
        Info: Total cell delay = 1.600 ns ( 54.72 % )
        Info: Total interconnect delay = 1.324 ns ( 45.28 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.703 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N13; Fanout = 1; REG Node = 'temp[2]~975'
        Info: 2: + IC(0.446 ns) + CELL(0.206 ns) = 0.652 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 3; COMB Node = 'temp[2]~976'
        Info: 3: + IC(1.835 ns) + CELL(3.216 ns) = 5.703 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'q2'
        Info: Total cell delay = 3.422 ns ( 60.00 % )
        Info: Total interconnect delay = 2.281 ns ( 40.00 % )
Info: Longest tpd from source pin "c" to destination pin "q2" is 12.742 ns
    Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_25; Fanout = 6; PIN Node = 'c'
    Info: 2: + IC(6.105 ns) + CELL(0.651 ns) = 7.691 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 3; COMB Node = 'temp[2]~976'
    Info: 3: + IC(1.835 ns) + CELL(3.216 ns) = 12.742 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'q2'
    Info: Total cell delay = 4.802 ns ( 37.69 % )
    Info: Total interconnect delay = 7.940 ns ( 62.31 % )
Info: th for register "temp[3]~973" (data pin = "x", clock pin = "cp") is -3.914 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.924 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
        Info: Total cell delay = 1.600 ns ( 54.72 % )
        Info: Total interconnect delay = 1.324 ns ( 45.28 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.144 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_43; Fanout = 2; PIN Node = 'x'
        Info: 2: + IC(5.732 ns) + CELL(0.370 ns) = 7.036 ns; Loc. = LCCOMB_X2_Y1_N30; Fanout = 1; COMB Node = 'temp[3]~982'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.144 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp[3]~973'
        Info: Total cell delay = 1.412 ns ( 19.76 % )
        Info: Total interconnect delay = 5.732 ns ( 80.24 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Nov 28 16:04:34 2007
    Info: Elapsed time: 00:00:00