shift.tan.qmsg

移位寄存器,异步清零,异步置数,左移右移可控,具有循环移位功能

{ "Info" "ITDB_FULL_TPD_RESULT" "c q2 12.742 ns Longest " "Info: Longest tpd from source pin \"c\" to destination pin \"q2\" is 12.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns c 1 PIN PIN_25 6 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_25; Fanout = 6; PIN Node = 'c'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "" { c } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.105 ns) + CELL(0.651 ns) 7.691 ns temp\[2\]~976 2 COMB LCCOMB_X2_Y1_N16 3 " "Info: 2: + IC(6.105 ns) + CELL(0.651 ns) = 7.691 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 3; COMB Node = 'temp\[2\]~976'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "6.756 ns" { c temp[2]~976 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.835 ns) + CELL(3.216 ns) 12.742 ns q2 3 PIN PIN_53 0 " "Info: 3: + IC(1.835 ns) + CELL(3.216 ns) = 12.742 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'q2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "5.051 ns" { temp[2]~976 q2 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.802 ns ( 37.69 % ) " "Info: Total cell delay = 4.802 ns ( 37.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.940 ns ( 62.31 % ) " "Info: Total interconnect delay = 7.940 ns ( 62.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "12.742 ns" { c temp[2]~976 q2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { c c~combout temp[2]~976 q2 } { 0.000ns 0.000ns 6.105ns 1.835ns } { 0.000ns 0.935ns 0.651ns 3.216ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp\[3\]~973 x cp -3.914 ns register " "Info: th for register \"temp\[3\]~973\" (data pin = \"x\", clock pin = \"cp\") is -3.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.924 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "" { cp } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.324 ns) + CELL(0.666 ns) 2.924 ns temp\[3\]~973 2 REG LCFF_X2_Y1_N31 1 " "Info: 2: + IC(1.324 ns) + CELL(0.666 ns) = 2.924 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp\[3\]~973'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "1.990 ns" { cp temp[3]~973 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.72 % ) " "Info: Total cell delay = 1.600 ns ( 54.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns ( 45.28 % ) " "Info: Total interconnect delay = 1.324 ns ( 45.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "2.924 ns" { cp temp[3]~973 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.924 ns" { cp cp~combout temp[3]~973 } { 0.000ns 0.000ns 1.324ns } { 0.000ns 0.934ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.144 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns x 1 PIN PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_43; Fanout = 2; PIN Node = 'x'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "" { x } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.732 ns) + CELL(0.370 ns) 7.036 ns temp\[3\]~982 2 COMB LCCOMB_X2_Y1_N30 1 " "Info: 2: + IC(5.732 ns) + CELL(0.370 ns) = 7.036 ns; Loc. = LCCOMB_X2_Y1_N30; Fanout = 1; COMB Node = 'temp\[3\]~982'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "6.102 ns" { x temp[3]~982 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.144 ns temp\[3\]~973 3 REG LCFF_X2_Y1_N31 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.144 ns; Loc. = LCFF_X2_Y1_N31; Fanout = 1; REG Node = 'temp\[3\]~973'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "0.108 ns" { temp[3]~982 temp[3]~973 } "NODE_NAME" } "" } } { "shift.vhd" "" { Text "C:/altera/quartus51/shift/shift.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 19.76 % ) " "Info: Total cell delay = 1.412 ns ( 19.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.732 ns ( 80.24 % ) " "Info: Total interconnect delay = 5.732 ns ( 80.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "7.144 ns" { x temp[3]~982 temp[3]~973 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.144 ns" { x x~combout temp[3]~982 temp[3]~973 } { 0.000ns 0.000ns 5.732ns 0.000ns } { 0.000ns 0.934ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "2.924 ns" { cp temp[3]~973 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.924 ns" { cp cp~combout temp[3]~973 } { 0.000ns 0.000ns 1.324ns } { 0.000ns 0.934ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shift" "UNKNOWN" "V1" "C:/altera/quartus51/shift/db/shift.quartus_db" { Floorplan "C:/altera/quartus51/shift/" "" "7.144 ns" { x temp[3]~982 temp[3]~973 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.144 ns" { x x~combout temp[3]~982 temp[3]~973 } { 0.000ns 0.000ns 5.732ns 0.000ns } { 0.000ns 0.934ns 0.370ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 16:04:34 2007 " "Info: Processing ended: Wed Nov 28 16:04:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}