📄 shift.fit.rpt
字号:
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 12.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
+---------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 3.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 1 Clock ; 1 ;
; 1 Clock enable ; 1 ;
+------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
Info: Processing started: Wed Nov 28 16:04:26 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shift -c shift
Info: Selected device EP2C5T144C8 for design "shift"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C5T144I8 is compatible
Info: Device EP2C8T144C8 is compatible
Info: Device EP2C8T144I8 is compatible
Info: Automatically promoted node temp[3]~983
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.611 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y1; Fanout = 1; REG Node = 'temp[2]~975'
Info: 2: + IC(0.675 ns) + CELL(0.206 ns) = 0.881 ns; Loc. = LAB_X2_Y1; Fanout = 3; COMB Node = 'temp[2]~976'
Info: 3: + IC(0.441 ns) + CELL(0.370 ns) = 1.692 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB No
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -