count.tan.rpt

模可变计数器,可实现模2模8模10模16,异步清零,模可变加减计数

; N/A   ; None         ; 5.552 ns   ; u    ; iq[2] ; cp       ;
; N/A   ; None         ; 5.547 ns   ; u    ; iq[1] ; cp       ;
; N/A   ; None         ; 4.783 ns   ; en   ; iq[3] ; cp       ;
; N/A   ; None         ; 4.783 ns   ; en   ; iq[0] ; cp       ;
; N/A   ; None         ; 4.783 ns   ; en   ; iq[1] ; cp       ;
; N/A   ; None         ; 4.783 ns   ; en   ; iq[2] ; cp       ;
+-------+--------------+------------+------+-------+----------+


+-------------------------------------------------------------+
; tco                                                         ;
+-------+--------------+------------+-------+----+------------+
; Slack ; Required tco ; Actual tco ; From  ; To ; From Clock ;
+-------+--------------+------------+-------+----+------------+
; N/A   ; None         ; 9.954 ns   ; iq[2] ; q2 ; cp         ;
; N/A   ; None         ; 9.881 ns   ; iq[0] ; q0 ; cp         ;
; N/A   ; None         ; 9.823 ns   ; iq[3] ; q3 ; cp         ;
; N/A   ; None         ; 9.441 ns   ; iq[1] ; q1 ; cp         ;
+-------+--------------+------------+-------+----+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -4.517 ns ; en   ; iq[3] ; cp       ;
; N/A           ; None        ; -4.517 ns ; en   ; iq[0] ; cp       ;
; N/A           ; None        ; -4.517 ns ; en   ; iq[1] ; cp       ;
; N/A           ; None        ; -4.517 ns ; en   ; iq[2] ; cp       ;
; N/A           ; None        ; -5.241 ns ; u    ; iq[2] ; cp       ;
; N/A           ; None        ; -5.244 ns ; u    ; iq[1] ; cp       ;
; N/A           ; None        ; -5.546 ns ; d0   ; iq[1] ; cp       ;
; N/A           ; None        ; -5.551 ns ; d0   ; iq[2] ; cp       ;
; N/A           ; None        ; -5.724 ns ; d1   ; iq[3] ; cp       ;
; N/A           ; None        ; -6.176 ns ; u    ; iq[3] ; cp       ;
; N/A           ; None        ; -6.437 ns ; d0   ; iq[3] ; cp       ;
; N/A           ; None        ; -6.603 ns ; d1   ; iq[2] ; cp       ;
; N/A           ; None        ; -6.606 ns ; d1   ; iq[1] ; cp       ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 29 19:32:52 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count -c count --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" has Internal fmax of 258.8 MHz between source register "iq[0]" and destination register "iq[1]" (period= 3.864 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y4_N19; Fanout = 8; REG Node = 'iq[0]'
        Info: 2: + IC(0.496 ns) + CELL(0.624 ns) = 1.120 ns; Loc. = LCCOMB_X2_Y4_N26; Fanout = 1; COMB Node = 'iq[2]~2607'
        Info: 3: + IC(0.687 ns) + CELL(0.651 ns) = 2.458 ns; Loc. = LCCOMB_X2_Y4_N2; Fanout = 2; COMB Node = 'iq[2]~2609'
        Info: 4: + IC(0.410 ns) + CELL(0.624 ns) = 3.492 ns; Loc. = LCCOMB_X2_Y4_N20; Fanout = 1; COMB Node = 'iq~2611'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.600 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq[1]'
        Info: Total cell delay = 2.007 ns ( 55.75 % )
        Info: Total interconnect delay = 1.593 ns ( 44.25 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "cp" to destination register is 2.934 ns
            Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
            Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq[1]'
            Info: Total cell delay = 1.600 ns ( 54.53 % )
            Info: Total interconnect delay = 1.334 ns ( 45.47 % )
        Info: - Longest clock path from clock "cp" to source register is 2.934 ns
            Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
            Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N19; Fanout = 8; REG Node = 'iq[0]'
            Info: Total cell delay = 1.600 ns ( 54.53 % )
            Info: Total interconnect delay = 1.334 ns ( 45.47 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "iq[1]" (data pin = "d1", clock pin = "cp") is 6.872 ns
    Info: + Longest pin to register delay is 9.846 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_42; Fanout = 3; PIN Node = 'd1'
        Info: 2: + IC(5.782 ns) + CELL(0.650 ns) = 7.366 ns; Loc. = LCCOMB_X2_Y4_N26; Fanout = 1; COMB Node = 'iq[2]~2607'
        Info: 3: + IC(0.687 ns) + CELL(0.651 ns) = 8.704 ns; Loc. = LCCOMB_X2_Y4_N2; Fanout = 2; COMB Node = 'iq[2]~2609'
        Info: 4: + IC(0.410 ns) + CELL(0.624 ns) = 9.738 ns; Loc. = LCCOMB_X2_Y4_N20; Fanout = 1; COMB Node = 'iq~2611'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 9.846 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq[1]'
        Info: Total cell delay = 2.967 ns ( 30.13 % )
        Info: Total interconnect delay = 6.879 ns ( 69.87 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N21; Fanout = 6; REG Node = 'iq[1]'
        Info: Total cell delay = 1.600 ns ( 54.53 % )
        Info: Total interconnect delay = 1.334 ns ( 45.47 % )
Info: tco from clock "cp" to destination pin "q2" through register "iq[2]" is 9.954 ns
    Info: + Longest clock path from clock "cp" to source register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N31; Fanout = 5; REG Node = 'iq[2]'
        Info: Total cell delay = 1.600 ns ( 54.53 % )
        Info: Total interconnect delay = 1.334 ns ( 45.47 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.716 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y4_N31; Fanout = 5; REG Node = 'iq[2]'
        Info: 2: + IC(3.680 ns) + CELL(3.036 ns) = 6.716 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'q2'
        Info: Total cell delay = 3.036 ns ( 45.21 % )
        Info: Total interconnect delay = 3.680 ns ( 54.79 % )
Info: th for register "iq[3]" (data pin = "en", clock pin = "cp") is -4.517 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_45; Fanout = 4; CLK Node = 'cp'
        Info: 2: + IC(1.334 ns) + CELL(0.666 ns) = 2.934 ns; Loc. = LCFF_X2_Y4_N7; Fanout = 3; REG Node = 'iq[3]'
        Info: Total cell delay = 1.600 ns ( 54.53 % )
        Info: Total interconnect delay = 1.334 ns ( 45.47 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.757 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_26; Fanout = 4; PIN Node = 'en'
        Info: 2: + IC(5.967 ns) + CELL(0.855 ns) = 7.757 ns; Loc. = LCFF_X2_Y4_N7; Fanout = 3; REG Node = 'iq[3]'
        Info: Total cell delay = 1.790 ns ( 23.08 % )
        Info: Total interconnect delay = 5.967 ns ( 76.92 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 29 19:32:52 2007
    Info: Elapsed time: 00:00:01