📄 count.tan.rpt
字号:
Timing Analyzer report for count
Thu Nov 29 19:32:52 2007
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'cp'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------+-------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.872 ns ; d1 ; iq[1] ; -- ; cp ; 0 ;
; Worst-case tco ; N/A ; None ; 9.954 ns ; iq[2] ; q2 ; cp ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.517 ns ; en ; iq[2] ; -- ; cp ; 0 ;
; Clock Setup: 'cp' ; N/A ; None ; 258.80 MHz ( period = 3.864 ns ) ; iq[0] ; iq[1] ; cp ; cp ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C8 ; ; ; ;
; Timing Models ; Preliminary ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; cp ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'cp' ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 258.80 MHz ( period = 3.864 ns ) ; iq[0] ; iq[1] ; cp ; cp ; None ; None ; 3.600 ns ;
; N/A ; 259.00 MHz ( period = 3.861 ns ) ; iq[0] ; iq[2] ; cp ; cp ; None ; None ; 3.597 ns ;
; N/A ; 278.40 MHz ( period = 3.592 ns ) ; iq[1] ; iq[1] ; cp ; cp ; None ; None ; 3.328 ns ;
; N/A ; 278.63 MHz ( period = 3.589 ns ) ; iq[1] ; iq[2] ; cp ; cp ; None ; None ; 3.325 ns ;
; N/A ; 294.64 MHz ( period = 3.394 ns ) ; iq[3] ; iq[1] ; cp ; cp ; None ; None ; 3.130 ns ;
; N/A ; 294.90 MHz ( period = 3.391 ns ) ; iq[3] ; iq[2] ; cp ; cp ; None ; None ; 3.127 ns ;
; N/A ; 323.42 MHz ( period = 3.092 ns ) ; iq[2] ; iq[1] ; cp ; cp ; None ; None ; 2.828 ns ;
; N/A ; 323.73 MHz ( period = 3.089 ns ) ; iq[2] ; iq[2] ; cp ; cp ; None ; None ; 2.825 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; iq[1] ; iq[3] ; cp ; cp ; None ; None ; 2.015 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; iq[2] ; iq[3] ; cp ; cp ; None ; None ; 1.811 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; iq[0] ; iq[3] ; cp ; cp ; None ; None ; 0.808 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; iq[0] ; iq[0] ; cp ; cp ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 360.10 MHz ( period = 2.777 ns ) ; iq[3] ; iq[3] ; cp ; cp ; None ; None ; 0.501 ns ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------+----------+
; N/A ; None ; 6.872 ns ; d1 ; iq[1] ; cp ;
; N/A ; None ; 6.869 ns ; d1 ; iq[2] ; cp ;
; N/A ; None ; 6.825 ns ; d0 ; iq[3] ; cp ;
; N/A ; None ; 6.562 ns ; u ; iq[3] ; cp ;
; N/A ; None ; 6.553 ns ; d0 ; iq[1] ; cp ;
; N/A ; None ; 6.550 ns ; d0 ; iq[2] ; cp ;
; N/A ; None ; 6.110 ns ; d1 ; iq[3] ; cp ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -