compare1.sim.rpt

这是一个定时比较器

; |counter|duty_load[5] ; |counter|duty_load[5] ; out              ;
; |counter|duty_load[6] ; |counter|duty_load[6] ; out              ;
; |counter|duty_load[7] ; |counter|duty_load[7] ; out              ;
; |counter|duty_load[8] ; |counter|duty_load[8] ; out              ;
; |counter|duty_load[9] ; |counter|duty_load[9] ; out              ;
; |counter|new_duty[1]  ; |counter|new_duty[1]  ; pin_out          ;
; |counter|new_duty[2]  ; |counter|new_duty[2]  ; pin_out          ;
; |counter|new_duty[3]  ; |counter|new_duty[3]  ; pin_out          ;
; |counter|new_duty[4]  ; |counter|new_duty[4]  ; pin_out          ;
; |counter|new_duty[5]  ; |counter|new_duty[5]  ; pin_out          ;
; |counter|new_duty[6]  ; |counter|new_duty[6]  ; pin_out          ;
; |counter|new_duty[8]  ; |counter|new_duty[8]  ; pin_out          ;
; |counter|Add0~55      ; |counter|Add0~55      ; out0             ;
; |counter|Add0~56      ; |counter|Add0~56      ; out0             ;
; |counter|Add0~57      ; |counter|Add0~57      ; out0             ;
; |counter|Add0~58      ; |counter|Add0~58      ; out0             ;
; |counter|Add0~59      ; |counter|Add0~59      ; out0             ;
; |counter|Add0~60      ; |counter|Add0~60      ; out0             ;
; |counter|Add0~61      ; |counter|Add0~61      ; out0             ;
; |counter|Add0~62      ; |counter|Add0~62      ; out0             ;
; |counter|Add0~63      ; |counter|Add0~63      ; out0             ;
; |counter|Add0~64      ; |counter|Add0~64      ; out0             ;
; |counter|Add0~65      ; |counter|Add0~65      ; out0             ;
; |counter|Add0~66      ; |counter|Add0~66      ; out0             ;
; |counter|Add0~67      ; |counter|Add0~67      ; out0             ;
; |counter|Add1~60      ; |counter|Add1~60      ; out0             ;
; |counter|Add1~61      ; |counter|Add1~61      ; out0             ;
; |counter|Add1~62      ; |counter|Add1~62      ; out0             ;
; |counter|Add1~63      ; |counter|Add1~63      ; out0             ;
; |counter|Add1~64      ; |counter|Add1~64      ; out0             ;
; |counter|Add1~65      ; |counter|Add1~65      ; out0             ;
; |counter|Add1~66      ; |counter|Add1~66      ; out0             ;
; |counter|Add1~67      ; |counter|Add1~67      ; out0             ;
; |counter|Add1~68      ; |counter|Add1~68      ; out0             ;
; |counter|Add1~69      ; |counter|Add1~69      ; out0             ;
; |counter|Add1~70      ; |counter|Add1~70      ; out0             ;
; |counter|Add1~71      ; |counter|Add1~71      ; out0             ;
; |counter|Add1~72      ; |counter|Add1~72      ; out0             ;
; |counter|Add1~73      ; |counter|Add1~73      ; out0             ;
; |counter|Add1~74      ; |counter|Add1~74      ; out0             ;
; |counter|Add1~75      ; |counter|Add1~75      ; out0             ;
; |counter|Add1~76      ; |counter|Add1~76      ; out0             ;
; |counter|Add1~77      ; |counter|Add1~77      ; out0             ;
; |counter|Add1~78      ; |counter|Add1~78      ; out0             ;
; |counter|Add1~79      ; |counter|Add1~79      ; out0             ;
; |counter|Add1~80      ; |counter|Add1~80      ; out0             ;
; |counter|Add1~81      ; |counter|Add1~81      ; out0             ;
; |counter|Add1~82      ; |counter|Add1~82      ; out0             ;
; |counter|Add1~84      ; |counter|Add1~84      ; out0             ;
; |counter|Add1~85      ; |counter|Add1~85      ; out0             ;
; |counter|Add1~87      ; |counter|Add1~87      ; out0             ;
+-----------------------+-----------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------+
; Missing 1-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |counter|temp~0        ; |counter|temp~0        ; out              ;
; |counter|temp~1        ; |counter|temp~1        ; out              ;
; |counter|temp1~0       ; |counter|temp1~0       ; out              ;
; |counter|temp1~1       ; |counter|temp1~1       ; out              ;
; |counter|temp1~2       ; |counter|temp1~2       ; out              ;
; |counter|temp1~3       ; |counter|temp1~3       ; out              ;
; |counter|temp1~11      ; |counter|temp1~11      ; out              ;
; |counter|temp1~23      ; |counter|temp1~23      ; out              ;
; |counter|temp[11]      ; |counter|temp[11]      ; out              ;
; |counter|temp[10]      ; |counter|temp[10]      ; out              ;
; |counter|temp[9]       ; |counter|temp[9]       ; out              ;
; |counter|temp1[11]     ; |counter|temp1[11]     ; regout           ;
; |counter|temp1[10]     ; |counter|temp1[10]     ; regout           ;
; |counter|temp1[9]      ; |counter|temp1[9]      ; regout           ;
; |counter|a1            ; |counter|a1            ; out              ;
; |counter|duty_load[10] ; |counter|duty_load[10] ; out              ;
; |counter|duty_load[11] ; |counter|duty_load[11] ; out              ;
; |counter|new_duty[9]   ; |counter|new_duty[9]   ; pin_out          ;
; |counter|new_duty[10]  ; |counter|new_duty[10]  ; pin_out          ;
; |counter|new_duty[11]  ; |counter|new_duty[11]  ; pin_out          ;
; |counter|Add0~68       ; |counter|Add0~68       ; out0             ;
; |counter|Add0~69       ; |counter|Add0~69       ; out0             ;
; |counter|Add0~70       ; |counter|Add0~70       ; out0             ;
; |counter|Add0~71       ; |counter|Add0~71       ; out0             ;
; |counter|Add0~72       ; |counter|Add0~72       ; out0             ;
; |counter|Add0~73       ; |counter|Add0~73       ; out0             ;
; |counter|Add1~83       ; |counter|Add1~83       ; out0             ;
; |counter|Add1~86       ; |counter|Add1~86       ; out0             ;
+------------------------+------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------+
; Missing 0-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |counter|temp1[0]      ; |counter|temp1[0]      ; regout           ;
; |counter|temp~0        ; |counter|temp~0        ; out              ;
; |counter|temp~1        ; |counter|temp~1        ; out              ;
; |counter|temp~4        ; |counter|temp~4        ; out              ;
; |counter|temp1~0       ; |counter|temp1~0       ; out              ;
; |counter|temp1~1       ; |counter|temp1~1       ; out              ;
; |counter|temp1~2       ; |counter|temp1~2       ; out              ;
; |counter|temp1~4       ; |counter|temp1~4       ; out              ;
; |counter|temp1~11      ; |counter|temp1~11      ; out              ;
; |counter|temp1~23      ; |counter|temp1~23      ; out              ;
; |counter|temp[11]      ; |counter|temp[11]      ; out              ;
; |counter|temp[10]      ; |counter|temp[10]      ; out              ;
; |counter|temp[9]       ; |counter|temp[9]       ; out              ;
; |counter|temp[7]       ; |counter|temp[7]       ; out              ;
; |counter|temp1[11]     ; |counter|temp1[11]     ; regout           ;
; |counter|temp1[10]     ; |counter|temp1[10]     ; regout           ;
; |counter|temp1[9]      ; |counter|temp1[9]      ; regout           ;
; |counter|temp1[7]      ; |counter|temp1[7]      ; regout           ;
; |counter|duty_load[10] ; |counter|duty_load[10] ; out              ;
; |counter|duty_load[11] ; |counter|duty_load[11] ; out              ;
; |counter|new_duty[0]   ; |counter|new_duty[0]   ; pin_out          ;
; |counter|new_duty[7]   ; |counter|new_duty[7]   ; pin_out          ;
; |counter|new_duty[9]   ; |counter|new_duty[9]   ; pin_out          ;
; |counter|new_duty[10]  ; |counter|new_duty[10]  ; pin_out          ;
; |counter|new_duty[11]  ; |counter|new_duty[11]  ; pin_out          ;
; |counter|Add0~68       ; |counter|Add0~68       ; out0             ;
; |counter|Add0~69       ; |counter|Add0~69       ; out0             ;
; |counter|Add0~70       ; |counter|Add0~70       ; out0             ;
; |counter|Add0~71       ; |counter|Add0~71       ; out0             ;
; |counter|Add0~72       ; |counter|Add0~72       ; out0             ;
; |counter|Add0~73       ; |counter|Add0~73       ; out0             ;
; |counter|Add1~83       ; |counter|Add1~83       ; out0             ;
; |counter|Add1~86       ; |counter|Add1~86       ; out0             ;
+------------------------+------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Oct 28 14:32:44 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off compare1 -c compare1
Info: Using vector source file "E:/mywork/new_compare/counter.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      74.26 %
Info: Number of transitions in simulation is 5955
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 92 megabytes of memory during processing
    Info: Processing ended: Sun Oct 28 14:32:47 2007
    Info: Elapsed time: 00:00:03