new_duty.qsf

这是一个定时比较器

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		new_duty_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE AUTO
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY dingshi1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:30:49  OCTOBER 24, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.vhd.bak
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.done
set_global_assignment -name EQUATION_FILE ../new_pwm/new_pwm.fit.eqn
set_global_assignment -name EQUATION_FILE ../new_pwm/new_pwm.map.eqn
set_global_assignment -name PIN_FILE ../new_pwm/new_pwm.pin
set_global_assignment -name PROGRAMMER_OBJECT_FILE ../new_pwm/new_pwm.pof
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm_assignment_defaults.qdf
set_global_assignment -name SOURCE_FILE ../new_pwm/prev_cmp_new_pwm.qmsg
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.qsf
set_global_assignment -name BSF_FILE ../new_pwm/new_pwm.bsf
set_global_assignment -name BDF_FILE ../new_pwm/load_control.bdf
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.qpf
set_global_assignment -name VECTOR_WAVEFORM_FILE ../new_pwm/new_pwm.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE ../new_pwm/Waveform1.vwf
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.qws
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.asm.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.eda.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.fit.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.flow.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.map.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.sim.rpt
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.tan.rpt
set_global_assignment -name SOURCE_FILE ../new_pwm/new_pwm.fit.smsg
set_global_assignment -name SRAM_OBJECT_FILE ../new_pwm/new_pwm.sof
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.fit.summary
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.map.summary
set_global_assignment -name TEXT_FORMAT_REPORT_FILE ../new_pwm/new_pwm.tan.summary
set_global_assignment -name VHDL_FILE ../new_pwm/new_pwm.vhd
set_global_assignment -name BDF_FILE "E:/mywork/new_compare/new_duty.bdf"
set_global_assignment -name VHDL_FILE counter.vhd
set_global_assignment -name BDF_FILE ../ram.bdf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE ../new_pwm/new_pwm.vwf
set_global_assignment -name VHDL_FILE compare1.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE ../dingshi/dingshi1.vhd