compare1.vhd.bak

这是一个定时比较器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity compare1 is
port(clk,en:in std_logic;
a1:in std_logic_vector(15 downto 0);
b1:in std_logic_vector(15 downto 0);
y1:out std_logic;
y2:out std_logic;
y3:out std_logic);
end compare1;

architecture one of compare1 is
signal temp1:std_logic_vector(15 downto 4);
signal temp2:std_logic_vector(15 downto 4);
begin
process(clk,a1,b1)
begin
temp1<=a1(15 downto 0);
temp2<=b1(15 downto 0); 
if rising_edge(clk) then
if en='1' then
if temp1<temp2 then
y1<='1';y2<='0';y3<='0';
elsif temp1=temp2 then
y2<='1';y1<='0';y3<='0';
else
y3<='1';y2<='0';y1<='0';
end if;
end if;
end if;
end process;
end one;