new_compare.vhd.bak

这是一个定时比较器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity new_compare is
port(clk:in std_logic;
a1:in std_logic_vector(11 downto 0);
b1:in std_logic_vector(11 downto 0);
duty_load:in std_logic_vector(11 downto 0);
new_duty:out std_logic_vector(11 downto 0));
end entity;

architecture one of new_compare is
signal temp: std_logic;
signal temp1: std_logic;
signal temp2: std_logic;
signal temp3: std_logic_vector(11 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (a1(11 downto 3) xor b1(11 downto 3))=0 then
if a1(2 downto 0)< b1(2 downto 0) then
temp<='1';
elsif a1(2 downto 0)= b1(2 downto 0) then
temp1<='1';
else
temp2<='1';
end if;
end if;
end if;
end process;

process(clk,temp,temp1,temp2)
begin
if temp1='1' then
temp3<="000000000000";
elsif temp1='0' then
temp3<=duty_load;
if rising_edge(clk) then
if temp='1' then
new_duty<=temp3+2;
end if;
if temp2='1' then
new_duty<=temp3-2;
end if;
end if;
end if;
end process;
end one;