prev_cmp_compare1.map.qmsg

这是一个定时比较器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 16:28:29 2007 " "Info: Processing started: Wed Oct 24 16:28:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off compare1 -c compare1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off compare1 -c compare1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "new_duty " "Warning: Ignored assignments for entity \"new_duty\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top " "Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "compare1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file compare1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 compare1-one " "Info: Found design unit 1: compare1-one" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 compare1 " "Info: Found entity 1: compare1" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-one " "Info: Found design unit 1: counter-one" {  } { { "counter.vhd" "" { Text "E:/mywork/new_compare/counter.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "E:/mywork/new_compare/counter.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "new_duty.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file new_duty.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 new_duty " "Info: Found entity 1: new_duty" {  } { { "new_duty.bdf" "" { Schematic "E:/mywork/new_compare/new_duty.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "new_duty " "Info: Elaborating entity \"new_duty\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst1\"" {  } { { "new_duty.bdf" "inst1" { Schematic "E:/mywork/new_compare/new_duty.bdf" { { 64 488 704 192 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "duty_load counter.vhd(18) " "Warning (10492): VHDL Process Statement warning at counter.vhd(18): signal \"duty_load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter.vhd" "" { Text "E:/mywork/new_compare/counter.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 counter.vhd(29) " "Warning (10492): VHDL Process Statement warning at counter.vhd(29): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter.vhd" "" { Text "E:/mywork/new_compare/counter.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compare1 compare1:inst " "Info: Elaborating entity \"compare1\" for hierarchy \"compare1:inst\"" {  } { { "new_duty.bdf" "inst" { Schematic "E:/mywork/new_compare/new_duty.bdf" { { 80 352 464 176 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a1 compare1.vhd(22) " "Warning (10492): VHDL Process Statement warning at compare1.vhd(22): signal \"a1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b1 compare1.vhd(23) " "Warning (10492): VHDL Process Statement warning at compare1.vhd(23): signal \"b1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a1 compare1.vhd(24) " "Warning (10492): VHDL Process Statement warning at compare1.vhd(24): signal \"a1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b1 compare1.vhd(25) " "Warning (10492): VHDL Process Statement warning at compare1.vhd(25): signal \"b1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "compare1.vhd" "" { Text "E:/mywork/new_compare/compare1.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "84 " "Info: Implemented 84 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "37 " "Info: Implemented 37 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Info: Implemented 35 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Allocated 154 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 16:28:38 2007 " "Info: Processing ended: Wed Oct 24 16:28:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}