compare1.map.rpt

这是一个定时比较器

; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                   ;
+----------------------------------+-----------------+-----------------+-----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path      ;
+----------------------------------+-----------------+-----------------+-----------------------------------+
; counter.vhd                      ; yes             ; User VHDL File  ; E:/mywork/new_compare/counter.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 25    ;
;                                             ;       ;
; Total combinational functions               ; 25    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 11    ;
;     -- 3 input functions                    ; 13    ;
;     -- <=2 input functions                  ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 10    ;
;                                             ;       ;
; Total registers                             ; 12    ;
;     -- Dedicated logic registers            ; 12    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 29    ;
; Maximum fan-out node                        ; a2    ;
; Maximum fan-out                             ; 13    ;
; Total fan-out                               ; 132   ;
; Average fan-out                             ; 2.00  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |counter                   ; 25 (25)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 29   ; 0            ; |counter            ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 11 bits   ; 22 LEs        ; 0 LEs                ; 22 LEs                 ; Yes        ; |counter|temp1[1]          ;
; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; No         ; |counter|temp[1]           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/mywork/new_compare/compare1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Oct 28 14:24:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off compare1 -c compare1
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-one
    Info: Found entity 1: counter
Info: Elaborating entity "counter" for the top level hierarchy
Info: Implemented 54 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 12 output pins
    Info: Implemented 25 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Sun Oct 28 14:24:53 2007
    Info: Elapsed time: 00:00:10