counter.vhd

来自「这是一个定时比较器」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(clk:in std_logic;
a1,a2,a3,en:in std_logic;
duty_load:in std_logic_vector(15 downto 0);
new_duty:out std_logic_vector(15 downto 0));
end entity;

architecture one of counter is
signal temp: std_logic_vector(15 downto 0);
signal temp1: std_logic_vector(15 downto 0);
begin
process(clk,en,temp1,duty_load,a2)
begin
if en='0' then
temp<=duty_load;
else
temp<=temp1;
end if;
if a2='1' then
temp<="0000000000000000";
elsif rising_edge(clk) then
if a1='1' then
temp1<=temp+2;
end if;
if a3='1' then
temp1<=temp-2;
end if;
end if;
new_duty<=temp1;
end process;
end one;