new_compare.sim.talkback.xml

这是一个定时比较器

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This XML file (created on Mon Nov 12 09:42:19 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>7.1</ver>
<schema>quartus_version_7.1_build_178.xsd</schema>
<license>
	<host_id>000475a7c517</host_id>
	<nic_id>000475a7c517</nic_id>
	<cdrive_id>dcec3435</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>7.1</version>
	<build>Build 178</build>
	<service_pack_label>1</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_sim</module>
	<edition>Web Edition</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Mon Nov 12 09:42:20 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1800</cpu_freq>
	</cpu>
	<ram units="MB">768</ram>
</machine>
<project>E:/mywork/new_compare/new_compare</project>
<revision>new_compare</revision>
<compilation_summary>
	<flow_status>Successful - Mon Nov 12 09:42:19 2007</flow_status>
	<simulator_setting_name>new_compare</simulator_setting_name>
	<top_level_entity_name>compare1</top_level_entity_name>
</compilation_summary>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off new_compare -c new_compare</command_line>
</mep_data>
<messages>
	<info>Info: Number of transitions in simulation is 18389</info>
	<info>Info: Simulation coverage is      75.83 %</info>
	<info>Info: Simulation partitioned into 1 sub-simulations</info>
	<info>Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled</info>
	<info>Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Functional</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Simulation results format</option>
		<setting>CVWF</setting>
	</row>
	<row>
		<option>Vector input source</option>
		<setting>Waveform.vwf</setting>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Display complete 1/0 value coverage report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Display missing 1-value coverage report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Display missing 0-value coverage report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate VCD File for PowerPlay Power Analyzer</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Trigger vector comparison with the specified mode</option>
		<setting>INPUT_EDGE</setting>
		<default_value>INPUT_EDGE</default_value>
	</row>
	<row>
		<option>Disable setup and hold time violations detection in input registers of bi-directional pins</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Perform Glitch Filtering in Timing Simulation</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>20.0 us</simulation_end_time>
	<simulation_netlist_size>120 nodes</simulation_netlist_size>
	<simulation_coverage>     75.83 %</simulation_coverage>
	<total_number_of_transitions>18389</total_number_of_transitions>
	<simulation_breakpoints>0</simulation_breakpoints>
	<family>Cyclone II</family>
</simulator_summary>
</talkback>