idt_512kx18_pbsram_test.v

verilog 写的 memory controller

tempcounter = 0;
 for (tempaddr=addr; tempaddr<addr+nburst; tempaddr=tempaddr+1) begin
   @( negedge CLK );
   if (tempaddr == addr) begin           // 1st address
      #(Tcyc/2 - Tsu);
      A     = addr;
      GW_   = 1;
      BWE_  = 1;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      ADV_  = 1;
      CE_   = ce_;
      CS1_  = cs1_;
      CS0   = cs0;
   end
   else begin
      #(Tcyc/2 - Tsu);                  // after 2nd address
      A     = 19'hz;
      ADV_ = 0;  
   end
    assign data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
   @( posedge CLK );      // SRAM latches Address and begins internal read
   lastaddr <= #(Tcyc) tempaddr;
   if (tempaddr == addr) begin           // 1st address
      A <= #Tdh 19'hz;
      ADSP_ <= #Tdh 1;
      ADSC_ <= #Tdh 1;
      CE_   <= #Tdh ~ce_;
      CS1_  <= #Tdh ~cs1_;
      CS0   <= #Tdh ~cs0;
      if(pipe == 1)
        OE_ <= #(Tcyc+Tcd-Toe) 0;
      if(pipe == 0)
        OE_ <= #(Tcd-Toe) 0;
   end
   else begin                            // after 2nd address
      ADV_  <= #Tdh 1;
   end
      if(pipe == 1)
        if(tempcounter > 1 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
      else if(pipe == 0)
        if(tempcounter > 0 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
    DQ = 18'hz;
    #Tdh;
    tempcounter = tempcounter+1;
 end
end
endtask

task burst_read_adv;       // ADSP|ADSC controlled - adsp/adsc 3-1-1-1 PL read
input  [addr_msb:0] addr;        //                        adsp/adsc 2-1-1-1 FT read
input  adsp_;
input  adsc_;
input  ce_; 
input  cs1_;
input  cs0; 
input  adv_;
input  [3:0] tempcounter;
begin
   @( negedge CLK );
   if (tempcounter == 0) begin            // 1st address
      #(Tcyc/2 - Tsu);
      A     = addr;
      GW_   = 1;
      BWE_  = 1;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      ADV_  = adv_;
      CE_   = ce_;
      CS1_  = cs1_;
      CS0   = cs0;
   end
   else begin
      #(Tcyc/2 - Tsu);                  // after 2nd address
      A     = 19'hz;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      CE_   = ce_;
      ADV_ = adv_;  
   end
    assign data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
   @( posedge CLK );      // SRAM latches Address and begins internal read
   lastaddr <= #(Tcyc) addr;
   if (tempcounter == 0) begin           // 1st address
      A <= #Tdh 19'hz;
      ADSP_ <= #Tdh ~adsp_;
      ADSC_ <= #Tdh ~adsc_;
      CE_   <= #Tdh ~ce_;
      CS1_  <= #Tdh ~cs1_;
      CS0   <= #Tdh ~cs0;
      if(pipe == 1)
        OE_ <= #(Tcyc+Tcd-Toe) 0;
      if(pipe == 0)
        OE_ <= #(Tcd-Toe) 0;
   end
   else begin                            // after 2nd address
      ADSP_ <= #Tdh ~adsp_;
      ADSC_ <= #Tdh ~adsc_;
      CE_   <= #Tdh ~ce_;
      ADV_  <= #Tdh ~adv_;
   end
      if(pipe == 1)
        if(tempcounter > 1 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
      else if(pipe == 0)
        if(tempcounter > 0 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
    DQ = 18'hz;
end
endtask

task read_random;
input  [addr_msb:0] addr;
output [17:0] data;
input  [17:0] exp;
begin
    if (CLK )
        @( negedge CLK );
//    DQ = 18'hz;
    ADV_  = 1;
    A = addr;
    ADSP_ = 0;
    @( posedge CLK );      // SRAM latches Address and begins internal read
    @( negedge CLK );
    ADSP_ = 1;
    OE_   = 0;
    if (pipe == 1) @( posedge CLK );      // SRAM begins placing data onto bus
    @( posedge CLK );      // Data sampled by reading device
                           // Hopefully the SRAM has an output hold time
    data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
    if ( data !== exp )
        $display("%d Read_random error: Addr %h Exp %h Act %h", $stime, addr, exp, data);
    @( negedge CLK ); 
    OE_   = 1;

end
endtask

task burst_read_random;   
input  [addr_msb:0] addr;
input  [17:0] n;
integer       i;
begin
    DQ = 18'hz;
    if ( CLK )
        @( negedge CLK );
    #1 A = addr;
       ADSP_ = 0;
    @( posedge CLK );           // Address latched by SRAM, begins internal read
    #(Tcyc/2) ADSP_ = 1;       // SRAM starts driving bus (flow-through)
    #1 OE_   = 0;
       ADV_  = 0;
    if (pipe == 1) @(posedge CLK); //SRAM starts driving bus (pipelined)
 
    for (i=addr;i<addr+n;i=i) begin
       @( posedge CLK ) begin
          if (check_data == 1) 
BurstData[i] = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
          if ( BurstData[i] !== RandomData[i] && check_data == 1 )
             $display("%d task burst_read_random read error: Addr %h Exp %h Act %h", $stime, i, RandomData[i], BurstData[i]);
       end
       @( negedge CLK );
       if (check_data) i=i+1;
       if ( ($random & 3) === 2'b11 ) // suspend burst 25% of the time
           ADV_ = 1;
       else begin
           ADV_ = 0;
       end
    end

    OE_   = 1;
    ADV_  = 1;
end
endtask

task burst_wrap_random; //checks burst counter wrap-around
input  [addr_msb:0] addr;
integer i,j;
begin
    DQ = 18'hz;
    if ( CLK )
       @( negedge CLK );
    #1 A = addr;
       ADSP_ = 0;
    @(posedge CLK);           // Address latched by SRAM, begins internal read
    #(Tcyc/2) ADSP_ = 1;
    #1 OE_   = 0;
       ADV_  = 0;
    if (pipe == 1) @(posedge CLK);
 
   for (i=0;i<2;i=i+1) begin
      for (j=0;j<4;j=j+1) begin
         @( posedge CLK ) begin
            if (check_data == 1) 
BurstData[j] = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
            if ( BurstData[j] !== RandomData[j] && check_data == 1 )
               $display("%d task burst_wrap_random read error: Addr %h Exp %h Act %h", $stime, i, RandomData[i], BurstData[i]);
         end
      end
   end
   #1 OE_   = 1;
      ADV_  = 1;
end
endtask

task burst_rd_pipe_random;
input  [addr_msb:0] addr1;
input  [addr_msb:0] addr2;

integer       i;

begin
   DQ = 18'hz;
   for (i=0;i<12;i=i+1) begin
      @(posedge CLK);

      if (i == 0 | i == 4) begin
         #(Tcyc/2) ADSP_ <= 0;
         if (i == 0) A = addr1;       
         if (i == 4) A = addr2;
      end   
      else #(Tcyc/2) ADSP_ <= 1;

      if (i >= 1 && i <=10) OE_ = 0;
      else OE_ = 1;

      if (i >= 1 && i <= 3 || i >= 5 && i<= 7) ADV_ <= 0;
      else ADV_ <= 1;
   end
end   
endtask

task write;        //ADSP|ADSC controlled PL|FT - adsp 2cycle/adsc 1cycle write   
input  [addr_msb:0] addr;
input  [17:0] data;
input  adsp_;  
input  adsc_; 
input  gw_;  
input  ce_; 
input  cs1_;
input  cs0; 
begin
   @( negedge CLK );
    A <= #(Tcyc/2-Tsu) addr;
    ADSP_ <= #(Tcyc/2-Tsu) adsp_;
    ADSC_ <= #(Tcyc/2-Tsu) adsc_;
    DQ = 18'hz;
    ADV_  = 1;
    CE_   <= #(Tcyc/2-Tsu) ce_;
    CS1_  <= #(Tcyc/2-Tsu) cs1_;
    CS0   <= #(Tcyc/2-Tsu) cs0;
    OE_   <= #(Tcyc/2-Tsu) 1;
    if (adsp_ == 0)                               // if adsp_ controlled
      GW_ = ~gw_;    
    else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
      #(Tcyc/2-Tsu)
      GW_ = gw_;
      DQ  = data;
        if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
          Dstore[addr] = data;
    end
    else
      DQ  = 18'hz;
   @( posedge CLK );
    counter = 0;
    A <= #Tdh 19'hz;
    ADSP_ <= #Tdh 1;
    ADSC_ <= #Tdh 1;
//    OE_   <= #Tdh 1;
    CE_   <= #Tdh 1;
    CS1_  <= #Tdh 1;
    CS0   <= #Tdh 0;
    if (adsp_ == 0) begin                         // if adsp controlled
      #(Tcyc - Tsu);
      GW_ = gw_;
      DQ = data;
//$display($time, "DQ    %h data  %d  addr %d", DQ, data, addr);
      GW_ <= #(Tsu + Tdh) ~gw_;
      DQ  <= #(Tsu + Tdh) 18'hz;
        if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
          Dstore[addr] = data;
    end
    else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
      GW_ <= #Tdh ~gw_;
      DQ  <= #Tdh 18'hz;
    end 
    else
      DQ  = 18'hz;
end
endtask

task burst_write;     //ADSP&ADSC controlled PL|FT - adsp_ 2-1-1-1/adsc_ 1-1-1-1 write   
input  [addr_msb:0] addr;
input  [17:0] data;
input  adsp_;
input  adsc_;
input  gw_;
input  ce_; 
input  cs1_;
input  cs0; 
input  [3:0] nburst;
integer tempaddr,tempcounter;
begin
tempcounter = 0;
 for (tempaddr=addr; tempaddr<addr+nburst; tempaddr=tempaddr+1) begin
   @( negedge CLK );
    DQ = 18'hz;
    if (tempaddr == addr) begin
        A <= #(Tcyc/2-Tsu) addr;
        ADSP_ <= #(Tcyc/2-Tsu) adsp_;
        ADSC_ <= #(Tcyc/2-Tsu) adsc_;
        ADV_   = 1;
        CE_   <= #(Tcyc/2-Tsu) ce_;
        CS1_  <= #(Tcyc/2-Tsu) cs1_;
        CS0   <= #(Tcyc/2-Tsu) cs0;
         if (adsp_ == 0) begin                        // if adsp_ controlled
           ADV_ = 1;
           GW_ = ~gw_;    
         end
         else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
           #(Tcyc/2-Tsu);
           GW_ = gw_;
           DQ  = data;
           if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
             Dstore[tempaddr] = data;
         end
         else
           DQ  = 18'hz;
    end
    else begin                                       // burst after 2nd cycle
        ADSP_ = 1;
        ADSC_ = 1;
        #(Tcyc/2-Tsu);
        GW_ = gw_;
        data = data+1;
        DQ  = data;
        if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
          Dstore[tempaddr] = data;
       if (tempcounter == 0) ADV_ = 1;
       else ADV_ = 0;
    end 
   @( posedge CLK );
    counter = 0;
    if (tempaddr == addr) begin
        A <= #Tdh 19'hz;
        ADSP_ <= #Tdh 1;
        ADSC_ <= #Tdh 1;
        OE_   <= #Tdh 1;
        CE_   <= #Tdh ~ce_;
        CS1_  <= #Tdh ~cs1_;
        CS0   <= #Tdh ~cs0;
         if (adsp_ == 0) begin                       // if adsp_ controlled
           #(Tcyc - Tsu);
           GW_ = gw_;
           DQ = data;
           ADV_ <= #(Tsu + Tdh) 1;
           GW_  <= #(Tsu + Tdh) ~gw_;
           DQ   <= #(Tsu + Tdh) 18'hz;
           if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
             Dstore[tempaddr] = data;
          if (tempcounter == 0) ADV_ = 1;
          else ADV_ = 0;
        end
        else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
           ADV_ <= #Tdh 1;
           GW_  <= #Tdh ~gw_;
           DQ   <= #Tdh 18'hz;
        end 
        else
           DQ  = 18'hz;
    end
    else begin                                        // burst after 2nd cycle
        ADV_ <= #Tdh 1;
        GW_  <= #Tdh ~gw_;
        DQ   <= #Tdh 18'hz;
    end
        tempcounter = tempcounter+1;
 end 
end
endtask

task burst_write_adv;   //ADSP|ADSC controlled PL|FT - adsp_ 2-1-1-1/adsc_ 1-1-1-1 write
input  [addr_msb:0] addr;
input  [17:0] data;
input  adsp_;
input  adsc_;
input  gw_;
input  ce_; 
input  cs1_;
input  cs0; 
input  adv_;
input  [3:0] tempcounter;
begin
   @( negedge CLK );
    DQ = 18'hz;
    if (tempcounter == 0) begin
        A <= #(Tcyc/2-Tsu) addr;
        ADSP_ <= #(Tcyc/2-Tsu) adsp_;
        ADSC_ <= #(Tcyc/2-Tsu) adsc_;
        ADV_   = adv_;
        CE_   <= #(Tcyc/2-Tsu) ce_;
        CS1_  <= #(Tcyc/2-Tsu) cs1_;
        CS0   <= #(Tcyc/2-Tsu) cs0;
         if (adsp_ == 0) begin                        // if adsp_ controlled
           ADV_ = adv_;
           GW_ = ~gw_;    
         end
         else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
           #(Tcyc/2-Tsu);
           GW_ = gw_;
           DQ  = data;
           if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
             Dstore[addr] = data;
         end
         else
           DQ  = 18'hz;
    end
    else begin                                       // burst after 2nd cycle
        ADSP_ = 1;
        ADSC_ = 1;
        #(Tcyc/2-Tsu);
        GW_ = gw_;
        ADV_ = adv_;
        DQ  = data;
        if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
          Dstore[addr] = data;
    end 
   @( posedge CLK );
    counter = 0;
    if (tempcounter == 0) begin
        A <= #Tdh 19'hz;
        ADSP_ <= #Tdh 1;
        ADSC_ <= #Tdh 1;
        OE_   <= #Tdh 1;
        CE_   <= #Tdh ~ce_;
        CS1_  <= #Tdh ~cs1_;
        CS0   <= #Tdh ~cs0;
         if (adsp_ == 0) begin                       // if adsp_ controlled
           #(Tcyc - Tsu);
           GW_ = gw_;
           DQ = data;
           ADV_ <= #(Tsu + Tdh) ~adv_;
           GW_  <= #(Tsu + Tdh) ~gw_;
           DQ   <= #(Tsu + Tdh) 18'hz;
           if (cs1_ == 0 & cs0 == 1 & ce_ == 0)
             Dstore[addr] = data;
           ADV_ = adv_;
        end
        else if (adsp_ == 1 & adsc_ == 0) begin       // if adsc_ controlled
           ADV_ <= #Tdh 1;
           GW_  <= #Tdh ~gw_;
           DQ   <= #Tdh 18'hz;
        end 
        else
           DQ  = 18'hz;
    end
    else begin                                        // burst after 2nd cycle
        ADV_ <= #Tdh 1;
        GW_  <= #Tdh ~gw_;
        DQ   <= #Tdh 18'hz;
    end
end
endtask

task write_random;
input  [addr_msb:0] addr;
input  [17:0] data;
begin
    if ( CLK )
        @( negedge CLK ); 
    OE_ = 1;
    ADV_  = 1;
    A = addr;
    ADSP_ = 0;
    @( negedge CLK );
    ADSP_ = 1;
    GW_ = 0;
    #(Tcyc/2-Tsu) DQ = data;
    @( posedge CLK );
    #Tdh
    DQ = 18'hz;
    @( negedge CLK );
    GW_ = 1;
end
endtask

task burst_write_random;
input  [addr_msb:0] addr;
input  [17:0] n;
integer       i;
begin
    if ( CLK )
        @( negedge CLK );
    #1 A = addr;
       ADSP_ = 0;
    for (i=addr;i<addr+n;i=i+1) begin
        @( negedge CLK );
        ADSP_ = 1;
        if (addr!=i) ADV_  = 0;
        #(Tcyc/2-Tsu) DQ = BurstData[i];
        @( posedge CLK );
    end
    @( negedge CLK );
    ADV_  = 1;
end
endtask

task byte_write_random;
input  [addr_msb:0] addr;
input  [17:0] data;
begin
    if ( CLK )
        @( negedge CLK );
    ADV_  = 1;
    A = addr;
    ADSP_ = 0;
    @( negedge CLK );
    ADSP_ = 1;
    BWE_ = 0;
    #(Tcyc/2-Tsu) DQ = data;
    @( posedge CLK );
    #Tdh
    DQ = 18'hz;
    @( negedge CLK );
    BWE_ = 1;
end
endtask

endmodule