wishbonemaster.vhd

模拟I2C EEPROM的VHDL代码。如常见的24c02等。

----------------------------------------------------------------------------------
-- Company:        Jacobs University Bremen - CWC Group
-- Engineer:       Mostafa Afgani
-- 
-- Create Date:    18:02:56 03/20/2007 
-- Design Name:   
-- Module Name:    WishBoneMaster - behavioral 
-- Project Name:   speed-estimator
-- Target Devices: ML402
-- Tool versions:  ISE 9.1.02i
-- Description: 	 A simple WISHBONE master for controlling the I2C core
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.06 - Revised state machine: state_{rd/wr}_ass
--                 removed to improve timing. Others renamed (remove _ass).
-- Revision 0.05 - Revised state machine: state_switch & state_wait_ack
--                 removed to improve timing
-- Revision 0.04 - Removed internal regs to prevent latches & added some
--                 constants to make code more readable
-- Revision 0.03 - Added default outputs and use (others => ) construct
-- Revision 0.02 - WISHBONE master, 1st implementation
-- Revision 0.01 - File Created
-- Additional Comments: 
--
-- $Id: WishBoneMaster.vhd 170 2007-04-19 16:11:36Z mafgani $
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity WishBoneMaster is
   Port (
		clk      : in 	std_logic;                    -- Clock signal
      rst		: in	std_logic;                    -- Reset (active low)
		
		adr		: out	std_logic_vector(2 downto 0);	-- Core register address
		din		: in	std_logic_vector(7 downto 0);	-- Data from core
		dout		: out	std_logic_vector(7 downto 0);	-- Data to core
		cyc		: out	std_logic;                    -- Bus cycle valid
		stb		: out	std_logic;                    -- Core select
		we		   : out	std_logic;                    -- Core write enable
		ack		: in	std_logic;                    -- ACK from core
		
		cmd		: in	std_logic;                    -- '0'-read, '1'-write
		addr		: in	std_logic_vector(2 downto 0);	-- Address to WISHBONE
		dati		: in	std_logic_vector(7 downto 0);	-- Data to WISHBONE
		dato		: out	std_logic_vector(7 downto 0);	-- Data from WISHBONE
		ready		: in	std_logic;                    -- Input data is valid
		done		: out	std_logic                     -- '1' - Core transactions complete
	);
end entity;

architecture behavioral of WishBoneMaster is
	type MachState is (
		state_idle,
		state_rd,
		state_wr
	);

-- Internal registers
signal state      : MachState;
signal next_state : MachState;

constant WR       : std_logic := '0';
constant RD       : std_logic := '1';
constant ARST_LVL : std_logic := '0';

begin

done              <= ack;
adr               <= addr;
dout              <= dati;
dato              <= din;


sync_state : process (clk)
begin
	if (clk'event and clk = '1') then
		if (rst = ARST_LVL) then
			state	            <= state_idle;
		else
			state             <= next_state;
		end if;
	end if;
end process sync_state;

outputs : process (state)
begin

	case (state) is
		when state_idle      =>
         cyc               <= '0';
         stb               <= '0';
         we                <= '0';
		when state_rd      	=>
			cyc               <= '1';
			stb               <= '1';
			we	               <= '0';
      when state_wr        =>
			cyc               <= '1';
			stb               <= '1';
			we                <= '1';
      when others          =>
         null;
	end case;

end process outputs;

change_state : process (state,ready,cmd,ack)
begin
	-- By default, stay in the current state
	next_state              <= state;

	case (state) is
		-- Idle state: state transition depends on command
		when state_idle      =>
			if (ready = '1') then
            if (cmd = RD) then
               next_state     <= state_rd;
            else
               next_state     <= state_wr;
            end if;
			end if;
      
		-- "Read" state: Assert necessary WISHBONE pins for the read op
      -- and change state only when ack is received
		when state_rd        =>
         if (ack = '1') then
            next_state        <=	state_idle;
         end if;
		
		-- "Write" state: Assert necessary WISHBONE pins for the write op
      -- and change state only when ack is received
		when state_wr        =>
         if (ack = '1') then
            next_state        <=	state_idle;
         end if;
		
		-- Error recovery
		when others          =>
			next_state           <= state_idle;
	end case;
   
end process change_state;

end architecture behavioral;