vhdl_delay.vhd

来自「模拟I2C EEPROM的VHDL代码。如常见的24c02等。」· VHDL 代码 · 共 40 行

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-- Company: 
-- Engineer: 
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-- Create Date:    14:42:34 03/31/2007 
-- Design Name: 
-- Module Name:    vhdl_delay - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vhdl_delay is
    Port ( inp : in  STD_LOGIC;
           outp : out  STD_LOGIC);
end vhdl_delay;

architecture Behavioral of vhdl_delay is
begin
   outp  <= transport inp after 600ns;
end Behavioral;