wbi2ctestbench.vhd

模拟I2C EEPROM的VHDL代码。如常见的24c02等。

--------------------------------------------------------------------------------
-- Company:        Jacobs University Bremen - CWC Group
-- Engineer:       Mostafa Afgani
--
-- Create Date:    12:15:01 03/27/2007
-- Design Name:    WishBoneMaster
-- Module Name:    WBi2cTestBench.vhd
-- Project Name:   speed-estimator
-- Target Devices: ML402
-- Tool versions:  ISE 9.1.02i
-- Description: 	 Testbench for the WISHBONE master and I2C core
-- 
-- VHDL Test Bench Created by ISE for module: WishBoneMaster
--
-- Dependencies:   WBi2cParams.vhd
-- 
-- Revision:
-- Revision 0.06 - Pullup added for delayed SCL/SDA, To_X01({sda_i/scl_i}) used
--                 for core SCL/SDA inputs
-- Revision 0.05 - Use 24Cxx I2C EEPROM as test slave
-- Revision 0.04 - Change I2C bus speed to 100kHz
-- Revision 0.03 - Re-introduce delays between commands
-- Revision 0.02 - Added separate scl_i and sda_i signals, took out delays
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
-- $Id: WBi2cTestBench.vhd 171 2007-04-19 18:49:58Z mafgani $
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

use work.WBi2cParams.all;

ENTITY WBi2cTestBench_vhd IS
END ENTITY WBi2cTestBench_vhd;

ARCHITECTURE behavior OF WBi2cTestBench_vhd IS 

	-- Component Declarations for the Unit Under Test (UUT)
	COMPONENT WishBoneMaster IS
	PORT(
		clk   : IN  std_logic;
		rst   : IN  std_logic;
		din   : IN  std_logic_vector(7 downto 0);
		ack   : IN  std_logic;
		cmd   : IN  std_logic;
		addr  : IN  std_logic_vector(2 downto 0);
		dati  : IN  std_logic_vector(7 downto 0);
		ready : IN  std_logic;          
		adr   : OUT std_logic_vector(2 downto 0);
		dout  : OUT std_logic_vector(7 downto 0);
		cyc   : OUT std_logic;
		stb   : OUT std_logic;
		we    : OUT std_logic;
		dato  : OUT std_logic_vector(7 downto 0);
		done  : OUT std_logic
		);
	END COMPONENT WishBoneMaster;
   
   COMPONENT i2c_master_top IS
	PORT(
		wb_clk_i       : IN  std_logic;
		wb_rst_i       : IN  std_logic;
		arst_i         : IN  std_logic;
		wb_adr_i       : IN  std_logic_vector(2 downto 0);
		wb_dat_i       : IN  std_logic_vector(7 downto 0);
		wb_we_i        : IN  std_logic;
		wb_stb_i       : IN  std_logic;
		wb_cyc_i       : IN  std_logic;
		scl_pad_i      : IN  std_logic;
		sda_pad_i      : IN  std_logic;          
		wb_dat_o       : OUT std_logic_vector(7 downto 0);
		wb_ack_o       : OUT std_logic;
		wb_inta_o      : OUT std_logic;
		scl_pad_o      : OUT std_logic;
		scl_padoen_o   : OUT std_logic;
		sda_pad_o      : OUT std_logic;
		sda_padoen_o   : OUT std_logic
		);
	END COMPONENT i2c_master_top;
   
   COMPONENT I2C_EEPROM is
   PORT(
      STRETCH        : IN    time;       --pull SCL low for this time-value;
      E0             : IN    std_logic;  --leave unconnected for 24C16, 24C08, 24C04
      E1             : IN    std_logic;  --leave unconnected for 24C16, 24C08
      E2             : IN    std_logic;  --leave unconnected for 24C16
      WC             : IN    std_logic;  --tie high to disable write mode
      SCL            : INOUT std_logic;
      SDA            : INOUT std_logic      
      );
   END COMPONENT I2C_EEPROM;

   COMPONENT vhdl_delay is
	PORT(
		inp   : IN  std_logic;          
		outp  : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk     :  std_logic := '0';
	SIGNAL rst     :  std_logic := '0';
	SIGNAL ack     :  std_logic := '0';
	SIGNAL cmd     :  std_logic := '0';
	SIGNAL ready   :  std_logic := '0';
	SIGNAL din     :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL addr    :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL dati    :  std_logic_vector(7 downto 0) := (others=>'0');

	SIGNAL adr     :  std_logic_vector(2 downto 0);
	SIGNAL dout    :  std_logic_vector(7 downto 0);
	SIGNAL cyc     :  std_logic;
	SIGNAL stb     :  std_logic;
	SIGNAL we      :  std_logic;
	SIGNAL dato    :  std_logic_vector(7 downto 0);
	SIGNAL done    :  std_logic;
   SIGNAL inta    :  std_logic;
   
   -- I2C BUS
   SIGNAL scl     :  std_logic;
   SIGNAL scl_i   :  std_logic := '0';
   SIGNAL scl_o   :  std_logic;
   SIGNAL scl_oe  :  std_logic;
   SIGNAL sda     :  std_logic;
   SIGNAL sda_i   :  std_logic := '0';
   SIGNAL sda_o   :  std_logic;
   SIGNAL sda_oe  :  std_logic;
   
   SIGNAL dSCL : std_logic;
   SIGNAL dSDA : std_logic;  
   
BEGIN
   
   clk_proc : process
   begin
      clk     <= '0';
      wait for PERIOD/2;
      clk     <= '1';
      wait for PERIOD/2;
	end process;
   
	-- Instantiations: WISHBONE Master
   uut1: WishBoneMaster PORT MAP(
		clk   => clk,
		rst   => rst,
		adr   => adr,
		din   => din,
		dout  => dout,
		cyc   => cyc,
		stb   => stb,
		we    => we,
		ack   => ack,
		cmd   => cmd,
		addr  => addr,
		dati  => dati,
		dato  => dato,
		ready => ready,
		done  => done
	);
   
   -- Instantiations: I2C Master Core
   uut2: i2c_master_top PORT MAP(
		wb_clk_i       => clk,
		wb_rst_i       => '0',
		arst_i         => rst,
		wb_adr_i       => adr,
		wb_dat_i       => dout,
		wb_dat_o       => din,
		wb_we_i        => we,
		wb_stb_i       => stb,
		wb_cyc_i       => cyc,
		wb_ack_o       => ack,
		wb_inta_o      => inta,
		scl_pad_i      => scl_i,
		scl_pad_o      => scl_o,
		scl_padoen_o   => scl_oe,
		sda_pad_i      => sda_i,
		sda_pad_o      => sda_o,
		sda_padoen_o   => sda_oe
	);
   
   uut3: I2C_EEPROM PORT MAP(
      STRETCH  => 5ns,
      E0       => 'L',
      E1       => 'L',
      E2       => 'L',
      WC       => 'L',
      SCL      => scl,
      SDA      => sda
   );
   
   scl_pullup : pullup PORT MAP (
      O     => scl
   );
   dscl_pullup: pullup PORT MAP (
      O     => dSCL
   );
   
   sda_pullup : pullup PORT MAP (
      O     => sda
   );   
   dsda_pullup: pullup PORT MAP (
      O     => dSDA
   );
   
   dSCL 				<=	scl_o when (scl_oe = '0') else 'Z';
   scl_i          <= To_X01(scl);         -- Core apparently does not understand 'H'
   dSDA 				<= sda_o when (sda_oe = '0') else 'Z';
   sda_i          <= To_X01(sda);         -- Core apparently does not understand 'H'
   
   mdSCL : vhdl_delay PORT MAP (
      inp         => dSCL,
      outp        => scl
   );
   
   mdSDA : vhdl_delay PORT MAP (
      inp         => dSDA,
      outp        => sda
   );
   
   tb : PROCESS
   
   variable buff     :  std_logic_vector(7 downto 0) := (others => '0');
   
   -- WISHBONE write
   procedure wb_wr (address : in std_logic_vector(2 downto 0);
                       data : in std_logic_vector(7 downto 0)) is
   begin
      ready    <= '0';
      cmd      <= WR;
      addr     <= address;
      dati     <= data;
      ready    <= '1';
      wait until done = '1';
      ready    <= '0';
      wait until (clk'event and clk = '1');
   end wb_wr;
   
   -- WISHBONE read
   procedure wb_rd (address : in  std_logic_vector(2 downto 0);
                       data : out std_logic_vector(7 downto 0)) is
   begin
      ready    <= '0';
      cmd      <= RD;
      addr     <= address;
      dati     <= (others => 'X');
      ready    <= '1';
      wait until done = '1';
      data     := dato;
      ready    <= '0';
      wait until (clk'event and clk = '1');
   end wb_rd;
   
   -- Check I2C core transfer-in-progress
   procedure i2c_chk_tip is
   variable datavec  :  std_logic_vector(7 downto 0) := (others => '0');
   begin
      wb_rd(SR, datavec);
      while (datavec(1) = '1') loop
         wb_rd(SR, datavec);
      end loop;
   end i2c_chk_tip;
   
	BEGIN
      
		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
      
      -- Reset the system
      rst   <= '1';
      wait for PERIOD;
      rst   <= '0';
      wait for PERIOD;
      rst   <= '1';
      
      -- Disbale core and verify
      wb_wr(CTR, X"00");
      wb_rd(CTR, buff);
      assert (buff = X"00") report "core not disabled" severity error;
      
      -- Program the core
      wb_wr(PRER_LO, X"c7");  -- clock PREscale Reg LO-byte (100 kHz)
      wb_wr(PRER_HI, X"00");  -- clock PREscale Reg HI-byte
      
      -- Verify
      wb_rd(PRER_LO, buff);
      assert (buff = X"c7") report "prer_lo fail" severity error;
      wb_rd(PRER_HI, buff);
      assert (buff = X"00") report "prer_hi fail" severity error;
      
      wb_wr(CTR, X"80");      -- ConTrol Reg, enable core
      wb_rd(CTR, buff);
      assert (buff = X"80") report "cannot enable core" severity error;
      
      
      -- ########################## --
      --       Write to slave       --
      -- ########################## --
      
      -- address the slave (write mode)
      wb_wr(TXR, SADR & WR);
--      wait for 20ns;
      wb_wr(CR, X"90");       -- command: start, write
--      wait for 20ns;
      
      -- check for TIP
      i2c_chk_tip;            -- blocks till TIP complete
      
--      wait for 15ns;
      wb_wr(TXR, X"00");      -- memory address
--      wait for 20ns;
      wb_wr(CR, X"10");       -- write
--      wait for 20ns;
      
      i2c_chk_tip;
--      wait for 20ns;
      
      wb_wr(TXR, X"A5");      -- data
--      wait for 20ns;
      wb_wr(CR, X"50");       -- stop, write
--      wait for 20ns;
      
      i2c_chk_tip;
--      wait for 20ns;
      
      wait for 20us;          -- wait
      
      wb_wr(TXR, SADR & WR);
--      wait for 20ns;
      wb_wr(CR, X"90");       -- command: start, write
--      wait for 20ns;
      
      i2c_chk_tip;
--      wait for 20ns;
      wb_wr(TXR, X"00");      -- memory address to read
--      wait for 20ns;
      wb_wr(CR, X"10");       -- write
--      wait for 20ns;
      
      i2c_chk_tip;
--      wait for 20ns;
      wb_wr(TXR, SADR & RD);
--      wait for 20ns;
      wb_wr(CR, X"90");       -- command: start, write
--      wait for 20ns;
      
      i2c_chk_tip;  
--      wait for 20ns;      
      
      wb_wr(CR, X"28");       -- command: read,nack_read
--      wait for 20ns;
      
      i2c_chk_tip;
--      wait for 20ns;
      
      wb_rd(RXR, buff);
      assert (buff = X"A5") report "wrong data" severity error;
		wait; -- will wait forever
	END PROCESS;

END ARCHITECTURE behavior;