key.vhd

来自「数字秒表的整个设计以及程序．波形仿真都在里面的了」· VHDL 代码 · 共 55 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY key  IS
PORT(
		clk,k  : IN	STD_LOGIC;
		en	   : OUT	STD_LOGIC
     );
END key;


ARCHITECTURE one OF key  IS
	type my_state is(s0,s1,s2,s3);
	SIGNAL state: my_state;
BEGIN
process(clk)
begin
    if clk'event and clk='1' then
       case state is
            when s0=>if k='1' then state<=s0;
                 else state<=s1;
                 end if;
            when s1=>if k='0' then state<=s1;
                 else state<=s2;
                 end if;
            when s2=>if k='1' then state<=s2;
                 else state<=s3;
                 end if;
             when s3=>if k='0' then state<=s3;
                 else state<=s0;
                 end if;
             when others=>null;
        end case;
     end if;
 end process;


process(clk)
begin
     if clk'event and clk='1' then
         case state is
             when s0=>en<='0';
             when s1=>en<='1';
             when s2=>en<='1';
             when s3=>en<='0';
             when others=>en<='0';
         end case;
      end if;
 end process;
END one;