fm.tan.qmsg

VHDL编写的驱动DDS

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\] register dds:inst\|data_reg\[13\] 132.64 MHz 7.539 ns Internal " "Info: Clock \"clk\" has Internal fmax of 132.64 MHz between source memory \"lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\]\" and destination register \"dds:inst\|data_reg\[13\]\" (period= 7.539 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.881 ns + Longest memory register " "Info: + Longest memory to register delay is 1.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\] 1 MEM M4K_X17_Y13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.468 ns) + CELL(0.309 ns) 1.881 ns dds:inst\|data_reg\[13\] 2 REG LC_X19_Y15_N2 1 " "Info: 2: + IC(1.468 ns) + CELL(0.309 ns) = 1.881 ns; Loc. = LC_X19_Y15_N2; Fanout = 1; REG Node = 'dds:inst\|data_reg\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.777 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] dds:inst|data_reg[13] } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.413 ns ( 21.96 % ) " "Info: Total cell delay = 0.413 ns ( 21.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.468 ns ( 78.04 % ) " "Info: Total interconnect delay = 1.468 ns ( 78.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.881 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] dds:inst|data_reg[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.881 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] dds:inst|data_reg[13] } { 0.000ns 1.468ns } { 0.104ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.971 ns - Smallest " "Info: - Smallest clock skew is -4.971 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.419 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FM.bdf" "" { Schematic "D:/FM/FM.bdf" { { -16 88 256 0 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns dds:inst\|clkdiv 2 REG LC_X8_Y10_N9 48 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 48; REG Node = 'dds:inst\|clkdiv'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk dds:inst|clkdiv } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.559 ns) + CELL(0.711 ns) 7.419 ns dds:inst\|data_reg\[13\] 3 REG LC_X19_Y15_N2 1 " "Info: 3: + IC(3.559 ns) + CELL(0.711 ns) = 7.419 ns; Loc. = LC_X19_Y15_N2; Fanout = 1; REG Node = 'dds:inst\|data_reg\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.270 ns" { dds:inst|clkdiv dds:inst|data_reg[13] } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.99 % ) " "Info: Total cell delay = 3.115 ns ( 41.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.304 ns ( 58.01 % ) " "Info: Total interconnect delay = 4.304 ns ( 58.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.419 ns" { clk dds:inst|clkdiv dds:inst|data_reg[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.419 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|data_reg[13] } { 0.000ns 0.000ns 0.745ns 3.559ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.390 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 12.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FM.bdf" "" { Schematic "D:/FM/FM.bdf" { { -16 88 256 0 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns dds:inst\|clkdiv 2 REG LC_X8_Y10_N9 48 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 48; REG Node = 'dds:inst\|clkdiv'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk dds:inst|clkdiv } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.520 ns) + CELL(0.935 ns) 7.604 ns dds:inst\|dds_fqud 3 REG LC_X8_Y11_N4 58 " "Info: 3: + IC(3.520 ns) + CELL(0.935 ns) = 7.604 ns; Loc. = LC_X8_Y11_N4; Fanout = 58; REG Node = 'dds:inst\|dds_fqud'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.455 ns" { dds:inst|clkdiv dds:inst|dds_fqud } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.708 ns) 12.390 ns lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\] 4 MEM M4K_X17_Y13 2 " "Info: 4: + IC(4.078 ns) + CELL(0.708 ns) = 12.390 ns; Loc. = M4K_X17_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.786 ns" { dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.047 ns ( 32.66 % ) " "Info: Total cell delay = 4.047 ns ( 32.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.343 ns ( 67.34 % ) " "Info: Total interconnect delay = 8.343 ns ( 67.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.390 ns" { clk dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.390 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } { 0.000ns 0.000ns 0.745ns 3.520ns 4.078ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.419 ns" { clk dds:inst|clkdiv dds:inst|data_reg[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.419 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|data_reg[13] } { 0.000ns 0.000ns 0.745ns 3.559ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.390 ns" { clk dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.390 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } { 0.000ns 0.000ns 0.745ns 3.520ns 4.078ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.708ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.881 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] dds:inst|data_reg[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.881 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] dds:inst|data_reg[13] } { 0.000ns 1.468ns } { 0.104ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.419 ns" { clk dds:inst|clkdiv dds:inst|data_reg[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.419 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|data_reg[13] } { 0.000ns 0.000ns 0.745ns 3.559ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.390 ns" { clk dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.390 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] } { 0.000ns 0.000ns 0.745ns 3.520ns 4.078ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.708ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk datain\[21\] lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\] 18.508 ns memory " "Info: tco from clock \"clk\" to destination pin \"datain\[21\]\" through memory \"lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\]\" is 18.508 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.390 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 12.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FM.bdf" "" { Schematic "D:/FM/FM.bdf" { { -16 88 256 0 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns dds:inst\|clkdiv 2 REG LC_X8_Y10_N9 48 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 48; REG Node = 'dds:inst\|clkdiv'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk dds:inst|clkdiv } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.520 ns) + CELL(0.935 ns) 7.604 ns dds:inst\|dds_fqud 3 REG LC_X8_Y11_N4 58 " "Info: 3: + IC(3.520 ns) + CELL(0.935 ns) = 7.604 ns; Loc. = LC_X8_Y11_N4; Fanout = 58; REG Node = 'dds:inst\|dds_fqud'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.455 ns" { dds:inst|clkdiv dds:inst|dds_fqud } "NODE_NAME" } } { "DDS.vhd" "" { Text "D:/FM/DDS.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.708 ns) 12.390 ns lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\] 4 MEM M4K_X17_Y13 2 " "Info: 4: + IC(4.078 ns) + CELL(0.708 ns) = 12.390 ns; Loc. = M4K_X17_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.786 ns" { dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.047 ns ( 32.66 % ) " "Info: Total cell delay = 4.047 ns ( 32.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.343 ns ( 67.34 % ) " "Info: Total interconnect delay = 8.343 ns ( 67.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.390 ns" { clk dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.390 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } { 0.000ns 0.000ns 0.745ns 3.520ns 4.078ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.468 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\] 1 MEM M4K_X17_Y13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|q_a\[21\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "D:/FM/db/altsyncram_jm21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.256 ns) + CELL(2.108 ns) 5.468 ns datain\[21\] 2 PIN PIN_94 0 " "Info: 2: + IC(3.256 ns) + CELL(2.108 ns) = 5.468 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'datain\[21\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.364 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] datain[21] } "NODE_NAME" } } { "FM.bdf" "" { Schematic "D:/FM/FM.bdf" { { 272 320 496 288 "datain\[31..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 40.45 % ) " "Info: Total cell delay = 2.212 ns ( 40.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.256 ns ( 59.55 % ) " "Info: Total interconnect delay = 3.256 ns ( 59.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] datain[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] datain[21] } { 0.000ns 3.256ns } { 0.104ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.390 ns" { clk dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.390 ns" { clk clk~out0 dds:inst|clkdiv dds:inst|dds_fqud lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] } { 0.000ns 0.000ns 0.745ns 3.520ns 4.078ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.708ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] datain[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[21] datain[21] } { 0.000ns 3.256ns } { 0.104ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 26 15:13:06 2005 " "Info: Processing ended: Sat Nov 26 15:13:06 2005" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}