📄 fm.sim.rpt
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; |FM|dds:inst|dds_data~728 ; |FM|dds:inst|dds_data~728 ; combout ;
; |FM|dds:inst|data_reg[9] ; |FM|dds:inst|data_reg[9] ; regout ;
; |FM|dds:inst|dds_data~729 ; |FM|dds:inst|dds_data~729 ; combout ;
; |FM|dds:inst|dds_data~731 ; |FM|dds:inst|dds_data~731 ; combout ;
; |FM|dds:inst|data_reg[8] ; |FM|dds:inst|data_reg[8] ; regout ;
; |FM|dds:inst|dds_data~732 ; |FM|dds:inst|dds_data~732 ; combout ;
; |FM|clk ; |FM|clk ; combout ;
; |FM|wclk ; |FM|wclk ; padio ;
; |FM|fqud ; |FM|fqud ; padio ;
; |FM|div_clk ; |FM|div_clk ; padio ;
; |FM|address[4] ; |FM|address[4] ; padio ;
; |FM|address[3] ; |FM|address[3] ; padio ;
; |FM|address[2] ; |FM|address[2] ; padio ;
; |FM|address[1] ; |FM|address[1] ; padio ;
; |FM|address[0] ; |FM|address[0] ; padio ;
; |FM|data_out[7] ; |FM|data_out[7] ; padio ;
; |FM|data_out[6] ; |FM|data_out[6] ; padio ;
; |FM|data_out[5] ; |FM|data_out[5] ; padio ;
; |FM|data_out[4] ; |FM|data_out[4] ; padio ;
; |FM|data_out[3] ; |FM|data_out[3] ; padio ;
; |FM|data_out[2] ; |FM|data_out[2] ; padio ;
; |FM|data_out[1] ; |FM|data_out[1] ; padio ;
; |FM|data_out[0] ; |FM|data_out[0] ; padio ;
; |FM|datain[14] ; |FM|datain[14] ; padio ;
; |FM|datain[13] ; |FM|datain[13] ; padio ;
; |FM|datain[12] ; |FM|datain[12] ; padio ;
; |FM|datain[11] ; |FM|datain[11] ; padio ;
; |FM|datain[10] ; |FM|datain[10] ; padio ;
; |FM|datain[9] ; |FM|datain[9] ; padio ;
; |FM|datain[8] ; |FM|datain[8] ; padio ;
; |FM|datain[7] ; |FM|datain[7] ; padio ;
; |FM|datain[6] ; |FM|datain[6] ; padio ;
; |FM|datain[5] ; |FM|datain[5] ; padio ;
; |FM|datain[4] ; |FM|datain[4] ; padio ;
; |FM|datain[3] ; |FM|datain[3] ; padio ;
; |FM|datain[2] ; |FM|datain[2] ; padio ;
; |FM|datain[1] ; |FM|datain[1] ; padio ;
; |FM|datain[0] ; |FM|datain[0] ; padio ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[6] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella6~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[6] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella6~COUTCOUT1_1 ; cout1 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella5~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella5~COUTCOUT1_1 ; cout1 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; portadataout0 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[29] ; portadataout1 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[28] ; portadataout2 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[27] ; portadataout3 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; portadataout4 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[18] ; portadataout6 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; portadataout0 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[26] ; portadataout1 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[25] ; portadataout2 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[20] ; portadataout6 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[16] ; portadataout8 ;
; |FM|dds:inst|data_reg[31] ; |FM|dds:inst|data_reg[31] ; regout ;
; |FM|dds:inst|data_reg[30] ; |FM|dds:inst|data_reg[30] ; regout ;
; |FM|dds:inst|data_reg[29] ; |FM|dds:inst|data_reg[29] ; regout ;
; |FM|dds:inst|data_reg[28] ; |FM|dds:inst|data_reg[28] ; regout ;
; |FM|dds:inst|data_reg[27] ; |FM|dds:inst|data_reg[27] ; regout ;
; |FM|dds:inst|data_reg[26] ; |FM|dds:inst|data_reg[26] ; regout ;
; |FM|dds:inst|data_reg[25] ; |FM|dds:inst|data_reg[25] ; regout ;
; |FM|reset ; |FM|reset ; padio ;
; |FM|address[7] ; |FM|address[7] ; padio ;
; |FM|address[6] ; |FM|address[6] ; padio ;
; |FM|datain[31] ; |FM|datain[31] ; padio ;
; |FM|datain[30] ; |FM|datain[30] ; padio ;
; |FM|datain[29] ; |FM|datain[29] ; padio ;
; |FM|datain[28] ; |FM|datain[28] ; padio ;
; |FM|datain[27] ; |FM|datain[27] ; padio ;
; |FM|datain[26] ; |FM|datain[26] ; padio ;
; |FM|datain[25] ; |FM|datain[25] ; padio ;
; |FM|datain[23] ; |FM|datain[23] ; padio ;
; |FM|datain[20] ; |FM|datain[20] ; padio ;
; |FM|datain[18] ; |FM|datain[18] ; padio ;
; |FM|datain[16] ; |FM|datain[16] ; padio ;
; |FM|dir[1] ; |FM|dir[1] ; padio ;
; |FM|dir[0] ; |FM|dir[0] ; padio ;
; |FM|oe[1] ; |FM|oe[1] ; padio ;
; |FM|oe[0] ; |FM|oe[0] ; padio ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
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