📄 fm.sim.rpt
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; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 64.97 % ;
; Total nodes checked ; 124 ;
; Total output ports checked ; 157 ;
; Total output ports with complete 1/0-value coverage ; 102 ;
; Total output ports with no 1/0-value coverage ; 39 ;
; Total output ports with no 1-value coverage ; 40 ;
; Total output ports with no 0-value coverage ; 54 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------+
; |FM|dds:inst|clkdiv ; |FM|dds:inst|clkdiv ; regout ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[4] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella4~COUT ; cout ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[3] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella3~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[3] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella3~COUTCOUT1 ; cout1 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[2] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella2~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[2] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella2~COUTCOUT1_1 ; cout1 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[1] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella1~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[1] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella1~COUTCOUT1_1 ; cout1 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[0] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella0~COUT ; cout0 ;
; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[0] ; |FM|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|counter_cella0~COUTCOUT1_1 ; cout1 ;
; |FM|dds:inst|dds_data[7] ; |FM|dds:inst|dds_data[7] ; regout ;
; |FM|dds:inst|dds_data[6] ; |FM|dds:inst|dds_data[6] ; regout ;
; |FM|dds:inst|dds_data[5] ; |FM|dds:inst|dds_data[5] ; regout ;
; |FM|dds:inst|dds_data[4] ; |FM|dds:inst|dds_data[4] ; regout ;
; |FM|dds:inst|dds_data[3] ; |FM|dds:inst|dds_data[3] ; regout ;
; |FM|dds:inst|dds_data[2] ; |FM|dds:inst|dds_data[2] ; regout ;
; |FM|dds:inst|dds_data[1] ; |FM|dds:inst|dds_data[1] ; regout ;
; |FM|dds:inst|dds_data[0] ; |FM|dds:inst|dds_data[0] ; regout ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[12] ; portadataout7 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[11] ; portadataout8 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[7] ; portadataout9 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[6] ; portadataout10 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[4] ; portadataout11 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[3] ; portadataout12 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[31] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[2] ; portadataout13 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; portadataout10 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[13] ; portadataout11 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[10] ; portadataout12 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[9] ; portadataout13 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[8] ; portadataout14 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[5] ; portadataout15 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[1] ; portadataout16 ;
; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; |FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[0] ; portadataout17 ;
; |FM|dds:inst|stat[0] ; |FM|dds:inst|stat[0] ; regout ;
; |FM|dds:inst|stat[3] ; |FM|dds:inst|stat[3] ; regout ;
; |FM|dds:inst|stat[2] ; |FM|dds:inst|stat[2] ; regout ;
; |FM|dds:inst|stat[1] ; |FM|dds:inst|stat[1] ; regout ;
; |FM|dds:inst|dds_wclk~142 ; |FM|dds:inst|dds_wclk~142 ; combout ;
; |FM|dds:inst|dds_fqud~83 ; |FM|dds:inst|dds_fqud~83 ; combout ;
; |FM|dds:inst|count[3] ; |FM|dds:inst|count[3] ; regout ;
; |FM|dds:inst|count[2] ; |FM|dds:inst|count[2] ; regout ;
; |FM|dds:inst|count[0] ; |FM|dds:inst|count[0] ; regout ;
; |FM|dds:inst|count[1] ; |FM|dds:inst|count[1] ; regout ;
; |FM|dds:inst|Equal0~19 ; |FM|dds:inst|Equal0~19 ; combout ;
; |FM|dds:inst|dds_data[7]~707 ; |FM|dds:inst|dds_data[7]~707 ; combout ;
; |FM|dds:inst|dds_data[7]~708 ; |FM|dds:inst|dds_data[7]~708 ; combout ;
; |FM|dds:inst|dds_data~709 ; |FM|dds:inst|dds_data~709 ; combout ;
; |FM|dds:inst|dds_data~710 ; |FM|dds:inst|dds_data~710 ; combout ;
; |FM|dds:inst|dds_data[7]~712 ; |FM|dds:inst|dds_data[7]~712 ; combout ;
; |FM|dds:inst|dds_data~713 ; |FM|dds:inst|dds_data~713 ; combout ;
; |FM|dds:inst|data_reg[14] ; |FM|dds:inst|data_reg[14] ; regout ;
; |FM|dds:inst|dds_data~714 ; |FM|dds:inst|dds_data~714 ; combout ;
; |FM|dds:inst|dds_data~716 ; |FM|dds:inst|dds_data~716 ; combout ;
; |FM|dds:inst|data_reg[13] ; |FM|dds:inst|data_reg[13] ; regout ;
; |FM|dds:inst|dds_data~717 ; |FM|dds:inst|dds_data~717 ; combout ;
; |FM|dds:inst|dds_data~719 ; |FM|dds:inst|dds_data~719 ; combout ;
; |FM|dds:inst|data_reg[12] ; |FM|dds:inst|data_reg[12] ; regout ;
; |FM|dds:inst|dds_data~720 ; |FM|dds:inst|dds_data~720 ; combout ;
; |FM|dds:inst|dds_data~722 ; |FM|dds:inst|dds_data~722 ; combout ;
; |FM|dds:inst|data_reg[11] ; |FM|dds:inst|data_reg[11] ; regout ;
; |FM|dds:inst|dds_data~723 ; |FM|dds:inst|dds_data~723 ; combout ;
; |FM|dds:inst|dds_data~725 ; |FM|dds:inst|dds_data~725 ; combout ;
; |FM|dds:inst|data_reg[10] ; |FM|dds:inst|data_reg[10] ; regout ;
; |FM|dds:inst|dds_data~726 ; |FM|dds:inst|dds_data~726 ; combout ;
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