plback_adv7179.v

deinterlace的核心verilog

    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
            begin
            dpr_rd_luma0_addr    <= 0;
            dpr_rd_luma1_addr    <= 0;
            end
        else if(col < 11'd289)
           begin
            dpr_rd_luma0_addr    <= 0;
            dpr_rd_luma1_addr    <= 0;
           end
        else if(col[0]==1'b1)
           begin
            dpr_rd_luma0_addr    <= dpr_rd_luma0_addr + 1;
            dpr_rd_luma1_addr    <= dpr_rd_luma1_addr + 1;
           end
    end
    
    always @(posedge dac_clk)
    begin
    
        if(sys_rstn==1'b0)
            dpr_rd_chroma_u_addr    <= 0;
        else if(col < 11'd289)
            dpr_rd_chroma_u_addr    <= 0;
        else if(col[1:0]==2'b01)
            dpr_rd_chroma_u_addr    <= dpr_rd_chroma_u_addr + 1;
    end
    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
            dpr_rd_chroma_v_addr    <= 0;
        else if(col < 11'd289)
            dpr_rd_chroma_v_addr    <= 0;
        else if(col[1:0]==2'b11)
            dpr_rd_chroma_v_addr    <= dpr_rd_chroma_v_addr + 1;
    end
    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
            de_start       <= 0;
        else if   ((col == 11'd1727) & (row == 10'd325 ))
                 begin
                 de_start <= 1'b1;
                 end  
        else if   ( odd_play_end )
                 begin
                   de_start   <= 0;
                 end      
    end
    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
        begin
            rd_buf_flag_dac <= 1'b0;
           
        end
        
        else if(((col == 11'd1727) & ((row > 10'd21) & (row < 10'd310)) & (row[1:0]==2'b01) & (~fill_odd_even)) |
                ((col == 11'd1727) & ((row > 10'd325) & (row < 10'd623)) & (row[1:0]==2'b10) &( fill_odd_even)))
            rd_buf_flag_dac <= ~rd_buf_flag_dac;
                 
            
    end
    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
        begin
            col <= 0;
            row <= 0;
        end
        else if(dac_enb)
        begin
            if(col == 11'd1727)
            begin
                col <= 0;
                
                if(row == 10'd624)
                    row <= 0;
                else
                    row <= row + 1;
            end
            else
            begin
                col <= col + 1;
            end
        end
    end
    
    always @(posedge dac_clk)
    begin
        if(sys_rstn==1'b0)
        begin
            dac_pa  <= 0;
        end
        else
        begin
            if((col == 11'd0)|(col == 11'd284))
                dac_pa <= 8'hff;
            else if((col == 11'd1) | (col == 11'd2) | (col == 11'd285) | (col == 11'd286))
                dac_pa <= 8'h0;
            else if((col == 11'd3) | (col == 11'd287))
                dac_pa <= xy;
            else if(((col > 11'd3) & (col < 11'd284))| (~(((row >= 10'd22)&(row <= 10'd309)) | ((row >= 10'd335)&(row <= 10'd622)))))
                if(col[0]==1'b0)
                    dac_pa  <= 8'h80;
                else
                    dac_pa  <= 8'h10;
            else if(col[0]==1'b1)
                    dac_pa <= luma;//{col[10:7],4'h0};//luma;
            else if(col[1]==1'b0)
                    dac_pa <= chroma_u;//{col[10:7],4'h0};//chroma_u;
            else 
                    dac_pa  <= chroma_v;//{col[10:7],4'h0};//chroma_v;
        end
    end
    
  //  reg filter_mode;
    //fill buf
    //always @(state,enc_start,rd_buf_flag,rd_buf_flag_d,fill_luma_over,fill_chroma_u_over,fill_chroma_v_over,dac_enb_p1)
    always @(posedge sys_clk)
    begin
        if((sys_rstn==1'b0)|(dac_start==1'b0))
        begin
            state   <= st_idle;
            
            dac_enb_cnt <= 0;
            dac_enb_p1  <= 0;
            dac_cmd_req_odd <= 0;
            fill_buf01  <= 0; 
            pass_chroma_cnt <= 0;
            col_cnt <= 0;
            row_cnt <= 0;
   //         ref_pic <= 0;
            fill_odd_even   <= 0;
            
            dac_cmd_addr_odd[18:0]  <= 0;
            //dac_cmd_addr_odd[20:19] <= dsp_ref_pic_base[1:0];
            dac_cmd_addr_odd[20:19] <= 0;
            dac_cmd_addr_odd[22:21] <= 2'b00; 
            line_cnt            <= 0;
            fill_cnt    <= 0; 
         //   de_start    <= 0;
        end
        else
        begin
           if  (  fill_odd_even == 1'b0  )
           begin
            case(state)
                st_idle:
                begin
                    if(enc_start)
                        state  <= st_wait;
                        
                    dac_cmd_req_odd <= 1'b0;
                end
                
                st_wait:
                begin
                    if((rd_buf_flag_d != rd_buf_flag) | (dac_enb_p1 == 1'b0))
                    begin
                        state  <= st_rd_luma;                        
                    end
                    col_cnt <= 0;    
                    dac_cmd_req_odd <= 1'b0;
                    fill_cnt    <= 0; 
                end
                
                st_rd_luma:
                begin
                      
                    if(fill_luma_over==1'b1)
                    begin
                        state   <= st_rd_chroma_u;
                        col_cnt <= 0;
                        fill_cnt    <= 0; 
                        
                        dac_cmd_addr_odd[18]    <= 1;
                        dac_cmd_addr_odd[9:0]   <= 0;
                        dac_cmd_addr_odd[17]    <= 0;
                        dac_cmd_addr_odd[16:10] <= line_cnt[7:1];
                    end
                    else
                    begin
                     
                        if(mpu_cmd_grant)
                            col_cnt <= col_cnt + 1;
                            
                        if(dac_cmd_enb_odd)
                        begin
                            dac_cmd_addr_odd[9:0]    <= dac_cmd_addr_odd[9:0] + 4;
                        end
                        
                        if(mpu_cmd_vld)
                            fill_cnt    <= fill_cnt + 1;
                     
                        
                    
                        if((col_cnt==8'd180)|mpu_cmd_grant )
                             dac_cmd_req_odd <= 1'b0;
                        else
                              dac_cmd_req_odd <= 1'b1;
                     end         
                 
       //        else
      //                  begin
      //                   de_start   <= 1'b1;  
                           
     //                    end         
                
                
                end
                
                st_rd_chroma_u:
                begin
                  
                    if(fill_chroma_u_over==1'b1)
                    begin
                        state  <= st_rd_chroma_v;
                        col_cnt <= 0;
                        fill_cnt    <= 0; 
                        
                        dac_cmd_addr_odd[9] <= 1'b1;
                        dac_cmd_addr_odd[8:0]   <= 0;
                    end
                    else//
                    begin
                        if(mpu_cmd_grant)
                            col_cnt <= col_cnt + 1;
                            
                        if(dac_cmd_enb_odd)
                        begin
                            dac_cmd_addr_odd[8:0]    <= dac_cmd_addr_odd[8:0] + 4;
                        end
                        
                        if(mpu_cmd_vld)
                            fill_cnt    <= fill_cnt + 1;
                    end
                        
                    if (pass_chroma_cnt[0]==1'b0)
                    begin           
                        if((col_cnt==8'd90)|mpu_cmd_grant )
                            dac_cmd_req_odd <= 1'b0;
                        else
                            dac_cmd_req_odd <= 1'b1;
                    end
                    else
                    begin
                        dac_cmd_req_odd <= 1'b0;
                    end
                 
               end 
             st_rd_chroma_v:
                
                   begin                  
                    if(fill_chroma_v_over==1'b1) 
                    begin
                        state  <= st_wait;
                        dac_enb_cnt <=  ~dac_enb_cnt;
                        fill_cnt    <= 0; 
                        
                        if(dac_enb_cnt == 1'b1)
                            dac_enb_p1  <= 1'b1;
                            
                        fill_buf01  <= ~fill_buf01; 
                        pass_chroma_cnt <= pass_chroma_cnt + 1;
                        col_cnt <= 0;
                        
                        if(row_cnt==7'd71   )
                        begin
                            row_cnt <= 0;
      //                      if(fill_odd_even)
      //                          ref_pic <= ref_pic + 1;
                            fill_odd_even   <= 1'b1;
         //                   de_start        <= 1'b1;
                        end
                        else
                        begin
                            row_cnt <= row_cnt + 1;
                        end
                        
              
                      if ((row_cnt == 7'd71 ))
                        begin
                        	dac_cmd_addr_odd[18:0]  <= 0;
                            line_cnt    <= 0;
                        end
                        else 
                        begin
                            line_cnt    <= line_cnt + 1;
                            dac_cmd_addr_odd[17:10] <= line_cnt + 1;//dac_cmd_addr_odd[17:10] + 1;
                            dac_cmd_addr_odd[9:0]   <= 0;
                            dac_cmd_addr_odd[18]    <= 0;//read luma
                        end
                    end
                    else//stay here
                    begin
                        if(mpu_cmd_grant)
                            col_cnt <= col_cnt + 1;
                            
                        if(dac_cmd_enb_odd)
                        begin
                            dac_cmd_addr_odd[8:0]    <= dac_cmd_addr_odd[8:0] + 4;
                        end
                        
                        if(mpu_cmd_vld)
                            fill_cnt    <= fill_cnt + 1;
                    end
                                 
                    if (pass_chroma_cnt[0]==1'b0)
                    begin           
                        if((col_cnt==8'd90)|mpu_cmd_grant )
                            dac_cmd_req_odd <= 1'b0;
                        else
                            dac_cmd_req_odd <= 1'b1;
                    end
                    else
                    begin
                        dac_cmd_req_odd <= 1'b0;
                    end
                    
              end
                
                default:
                begin
                    state  <= st_idle;
                end
            endcase
          end
          
      else
        begin
           
        if ( odd_play_end )
           begin
             if(dac_cmd_addr_odd[20:19]!=(dsp_ref_pic_ptr[1:0] - 2'b01))
                 begin
                           dac_cmd_addr_odd[20:19] <= dac_cmd_addr_odd[20:19] + 1;
                           dac_cmd_addr_odd[18:0]  <= 0;
                           line_cnt    <= 0;
                 end
              fill_odd_even   <= 1'b0; 
         //     de_start        <= 0;             
           end
        end
       end    
     end
    
   
  
    

    
    always @(posedge sys_clk)
    begin
        if(sys_rstn==1'b0)
        begin