plback_adv7179.v

deinterlace的核心verilog

// FileName     :   plback_adv7179.v
// Module Name  :   plback_adv7179
// Created      :   2006.07.26
// Last Updated :   2006.08.02
// Creator      :   wangyuelong
// Description  :
//      Pass reframe to adv7179 with ITU-R BT.656 pattern
// modify by zhangchi  2007.02.27
`timescale 1ns/1ns
module plback_adv7179(
    sys_clk,
    sys_rstn,
    
    dac_clk,
    dac_pa,
    dac_start,
    
    dac_cmd_req,
    dac_cmd_enb,
    dac_cmd_addr,
    dac_cmd_len,
    dac_cmd_rwn,
    
    mpu_cmd_grant,
    mpu_cmd_data,
    mpu_cmd_vld,
    
    dsp_ref_pic_max,
    dsp_ref_pic_lu,
    dsp_ref_pic_chm,
    dsp_ref_pic_base,
    dsp_ref_pic_ptr,
    
    hsync,
    vsync,
    test_port
    );
    
    input           sys_clk;
    input           sys_rstn;
    
    input           dac_clk;//27M
    input           dac_start;//reference frame is ready
    output  [7:0]   dac_pa;//output to DA
    
    output          dac_cmd_req;
    output          dac_cmd_enb;
    output   [22:0] dac_cmd_addr;    output   [1:0]  dac_cmd_len;
    output          dac_cmd_rwn;
    
    input           mpu_cmd_grant;
    input   [31:0]  mpu_cmd_data;
    input           mpu_cmd_vld;
    
    input   [1:0]   dsp_ref_pic_max;
    input           dsp_ref_pic_lu;
    input           dsp_ref_pic_chm;
    input   [1:0]   dsp_ref_pic_base;
    input   [1:0]   dsp_ref_pic_ptr;
    output          hsync;
    output          vsync;
    output  [31:0]  test_port;
    
    assign  hsync = 1'b0;
    assign  vsync = 1'b0;
    
    reg     [10:0]  col;
    reg     [9:0]   row;
    reg             dac_enb,dac_enb_p0,dac_enb_p1;
    reg             dac_enb_cnt;
    reg     [7:0]   dac_pa;
    
  //  reg     [1:0]   ref_pic;
    reg             dac_cmd_req;
    reg             dac_cmd_enb;
    reg     [22:0]  dac_cmd_addr;
    reg             dac_cmd_req_odd;
    reg             dac_cmd_enb_odd;
    reg     [22:0]  dac_cmd_addr_odd;
    
    reg             rd_buf_flag,rd_buf_flag_d,rd_buf_flag_p;
    reg             rd_buf_flag_dac;
    reg     [9:0]   dpr_rd_luma0_addr;
    reg     [9:0]   dpr_wr_luma0_addr;
    reg     [9:0]   dpr_rd_luma1_addr;
    reg     [9:0]   dpr_wr_luma1_addr;
    reg             dpr_wr_luma_enb0,dpr_wr_luma_enb1,dpr_wr_luma_enb2,dpr_wr_luma_enb3;
    reg     [31:0]  dpr_wr_data;
   
    
    reg     [15:0]  dpr_wr_lu0_data;
    reg     [15:0]  dpr_wr_lu1_data;
    
    reg     [8:0]   dpr_wr_chroma_u_addr;
    reg             dpr_wr_chroma_u_enb0;
    reg             dpr_wr_chroma_u_enb1;
    reg     [8:0]   dpr_rd_chroma_u_addr;
    
    reg     [8:0]   dpr_wr_chroma_v_addr;
    reg             dpr_wr_chroma_v_enb0;
    reg             dpr_wr_chroma_v_enb1;
    reg     [8:0]   dpr_rd_chroma_v_addr;
    
    reg     [2:0]   state,next_state;
    parameter   [2:0]   st_idle         = 3'd0,
                        st_wait         = 3'd1,
                        st_rd_luma      = 3'd2,
                        st_rd_chroma_u  = 3'd3,
                        st_rd_chroma_v  = 3'd4;
    
    reg     [7:0]   col_cnt;
    reg     [6:0]   row_cnt;
    reg             fill_odd_even;//0-even,1-odd
    reg             fill_buf01;
    reg             fill_luma_over,fill_chroma_u_over,fill_chroma_v_over;
    reg     [9:0]   fill_cnt;
    reg     [1:0]   pass_chroma_cnt;
    reg     [5:0]   mb_x,mb_y;
    reg     [7:0]   line_cnt;
    reg     [11:0]  time_cnt;
    
    reg             fill_odd_over;
    
    reg             de_start;
    wire[1:0]       de_row_flag;
    wire            de_luma_vld;
    wire            de_u_vld;
    wire            de_v_vld;
    wire            odd_play_end;
    wire[2:0]       de_write_st;
    
    
    wire            timeout;
             
    wire    [15:0]  luma0,luma1,luma2,luma3;
    wire    [31:0]  chroma_u0,chroma_u1; 
    wire    [31:0]  chroma_v0,chroma_v1;          
    reg     [7:0]   luma,chroma_u,chroma_v;
    wire            enc_start;
    reg             xy_f,xy_v,xy_h;
    wire            xy_p0,xy_p1,xy_p2,xy_p3;
    wire    [7:0]   xy;
    assign  xy_p3 = xy_v ^ xy_h;
    assign  xy_p2 = xy_f ^ xy_h;
    assign  xy_p1 = xy_f ^ xy_v;
    assign  xy_p0 = xy_f ^ xy_v ^ xy_h;
    assign  xy = {1'b1,xy_f,xy_v,xy_h,xy_p3,xy_p2,xy_p1,xy_p0};
    
    assign  enc_start = dac_start;
    assign  dac_cmd_len = 2'b11;
    assign  dac_cmd_rwn = 1'b1;//always read
    
    assign  timeout = time_cnt == 12'hfff;
   
    assign  test_port[31:13] = dac_cmd_addr_odd[18:0];
    assign  test_port[12:9]    =    mpu_cmd_data[31:28];
    assign  test_port[8]    = timeout;
    assign  test_port[7:5]  = state[2:0];
    assign  test_port[4:1]  = {mpu_cmd_vld,dac_cmd_enb_odd,mpu_cmd_grant,dac_cmd_req_odd};
    assign  test_port[0]    = fill_chroma_u_over;//dac_clk;//(state == st_wait) & (next_state == st_rd_luma);
    
    wire    deint_cmd_req_t;
    wire    deint_cmd_enb_t;
    wire[22:0]  deint_cmd_addr_t;
    wire[31:0]  de_out_lu_data;
    wire[31:0]  de_out_u_data;
    wire[31:0]  de_out_v_data;
    wire        de_out_luma_enb;
    wire        de_out_u_enb;
    wire        de_out_v_enb;
    
    wire        lowest_lu_enb; 
    wire        lowest_u_enb; 
    wire        lowest_v_enb; 
    
   
    
    always @ ( fill_odd_even,dac_cmd_req_odd,dac_cmd_enb_odd,dac_cmd_addr_odd,deint_cmd_req_t,deint_cmd_enb_t, deint_cmd_addr_t)
       begin
        
             if ( fill_odd_even == 1'b0 )
               begin
                  dac_cmd_req  <= dac_cmd_req_odd ;
                  dac_cmd_enb  <= dac_cmd_enb_odd;
                  dac_cmd_addr[22:0]  <= dac_cmd_addr_odd[22:0];
               end
             else
               begin
                  dac_cmd_req  <= deint_cmd_req_t ;
                  dac_cmd_enb  <= deint_cmd_enb_t;
                  dac_cmd_addr[22:0]  <= deint_cmd_addr_t[22:0];
               end 
       end
     
    // chipscope insert
    
//     wire [35:0] chipscope_icon_1_control0;
//     wire [31:0] scope_data;
//   ila
//    chipscope_ila (
//      .control ( chipscope_icon_1_control0 ),
//      .clk ( sys_clk ),
//      .trig0 (scope_data )
 //   );

 ///icon
 //   chipscope_icon (
 //     .control0 ( chipscope_icon_1_control0 )
//    );

//    assign    scope_data[31:16] = de_out_lu_data[31:16];
//    assign    scope_data[15:8] = de_out_u_data[31:24];
//    assign    scope_data[7] = de_luma_vld;
//    assign    scope_data[6] = de_start;
//    assign    scope_data[5] = lowest_lu_enb;
 //   assign    scope_data[4] = fill_odd_even;
 //   assign    scope_data[3] = dac_cmd_req_odd;
    
     de_inter   de_inter (
              
               .sys_clk ( sys_clk ),
               .sys_rstn ( sys_rstn ),
               .mpu_cmd_grant( mpu_cmd_grant),
               .mpu_cmd_data ( mpu_cmd_data),
               .mpu_cmd_vld( mpu_cmd_vld),
               .deint_cmd_req( deint_cmd_req_t ),
               .deint_cmd_enb( deint_cmd_enb_t),
               .deint_cmd_addr( deint_cmd_addr_t),
               .de_start  ( de_start ),
               .de_luma_vld ( de_luma_vld),
               .de_u_vld ( de_u_vld ),
               .de_v_vld ( de_v_vld ),
               .de_row_flag ( de_row_flag ),
               .odd_play_end ( odd_play_end ),
               .de_out_lu_data ( de_out_lu_data),
               .de_out_u_data ( de_out_u_data ),
               .de_out_v_data ( de_out_v_data ),
               .de_out_luma_enb ( de_out_luma_enb ),
               .de_out_u_enb ( de_out_u_enb ),
               .de_out_v_enb ( de_out_v_enb ),
               .lowest_lu_enb ( lowest_lu_enb ),
               .lowest_u_enb ( lowest_u_enb ),
               .lowest_v_enb ( lowest_v_enb ),
               .rd_buf_flag ( rd_buf_flag),
               .rd_buf_flag_d ( rd_buf_flag_d )
               
               
     
                   );
     
 
    always @(row, luma0,luma1,luma2,luma3)
    begin
        if(row <= 10'd309) 
            case(row[2:0])
                3'b000: luma <= luma1[15:8];
                3'b001: luma <= luma1[7:0];
                3'b010: luma <= luma2[15:8];
                3'b011: luma <= luma2[7:0];
                
                3'b100: luma <= luma3[15:8];
                3'b101: luma <= luma3[7:0];
                3'b110: luma <= luma0[15:8];
                3'b111: luma <= luma0[7:0];
                
            endcase
        else
            case(row[2:0])
                3'b000: luma <= luma0[7:0];
                3'b001: luma <= luma1[15:8];
                3'b010: luma <= luma1[7:0];
                3'b011: luma <= luma2[15:8];
                
                3'b100: luma <= luma2[7:0];
                3'b101: luma <= luma3[15:8];
                3'b110: luma <= luma3[7:0];
                3'b111: luma <= luma0[15:8];
                
            endcase
    end
    
    always @(row, chroma_u0,chroma_u1)
    begin
        if(row <= 10'd309) 
            case(row[2:0])
                3'b000: chroma_u    <= chroma_u0[15:8];
                3'b001: chroma_u    <= chroma_u0[7:0];
                3'b010: chroma_u    <= chroma_u1[31:24];
                3'b011: chroma_u    <= chroma_u1[23:16];
                3'b100: chroma_u    <= chroma_u1[15:8];
                3'b101: chroma_u    <= chroma_u1[7:0];
                3'b110: chroma_u    <= chroma_u0[31:24];
                3'b111: chroma_u    <= chroma_u0[23:16];
            endcase
        else
            case(row[2:0])
                3'b000: chroma_u    <= chroma_u0[23:16];
                3'b001: chroma_u    <= chroma_u0[15:8];
                3'b010: chroma_u    <= chroma_u0[7:0];
                3'b011: chroma_u    <= chroma_u1[31:24];
                3'b100: chroma_u    <= chroma_u1[23:16];
                3'b101: chroma_u    <= chroma_u1[15:8];
                3'b110: chroma_u    <= chroma_u0[7:0];
                3'b111: chroma_u    <= chroma_u0[31:24];
            endcase
    end
    
    always @(row, chroma_v0,chroma_v1)
    begin
        if(row <= 10'd309) 
            case(row[2:0])
                3'b000: chroma_v    <= chroma_v0[15:8];
                3'b001: chroma_v    <= chroma_v0[7:0];
                3'b010: chroma_v    <= chroma_v1[31:24];
                3'b011: chroma_v    <= chroma_v1[23:16];
                3'b100: chroma_v    <= chroma_v1[15:8];
                3'b101: chroma_v    <= chroma_v1[7:0];
                3'b110: chroma_v    <= chroma_v0[31:24];
                3'b111: chroma_v    <= chroma_v0[23:16];
            endcase
        else
            case(row[2:0])
                3'b000: chroma_v    <= chroma_v0[23:16];
                3'b001: chroma_v    <= chroma_v0[15:8];
                3'b010: chroma_v    <= chroma_v0[7:0];
                3'b011: chroma_v    <= chroma_v1[31:24];
                3'b100: chroma_v    <= chroma_v1[23:16];
                3'b101: chroma_v    <= chroma_v1[15:8];
                3'b110: chroma_v    <= chroma_v0[7:0];
                3'b111: chroma_v    <= chroma_v0[31:24];
            endcase
    end
    
    always @(row)
    begin
        if(row < 10'd312)
            xy_f    <= 0;
        else
            xy_f    <= 1;
    end
    
    always @(row)
    begin
        if(((row >= 10'd22)&(row <= 10'd309)) | ((row >= 10'd335)&(row <= 10'd622)))
            xy_v    <= 0;
        else
            xy_v    <= 1;
    end
    
    always @(col)
    begin
        if(col < 11'd4)
            xy_h    <= 1;
        else
            xy_h    <= 0;
    end
    
    //output fsm
    always @(posedge dac_clk)
    begin
        dac_enb     <= dac_enb_p0;
        dac_enb_p0  <= dac_enb_p1;
    end