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📄 de_inter.v

📁 deinterlace的核心verilog
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                                    end
                                 end   
                              else
                                begin
                                
                                 if ( u_rd_cnt == 9'd360 )
                                   begin
                              
                                  de_dly1_flag    <= de_dly_flag;
                                                    
                                  end  
                                 if ( de_dly1_flag )
                              
                                    begin
                                     de_write_st  <= de_v_write0;
                                     
                                     deint_cmd_addr[9] <= 1'b1;
                                     deint_cmd_addr[8:0]   <= 0;
                                     de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                              
                                    end
                                 end   
                               
              
                           end
                de_u_write1:  begin
                              if ( mpu_cmd_vld ) 
                               
                                begin
                                  dpr_wr_u1_addr  <= dpr_wr_u1_addr  +1;
                                  dpr_wr_u1_data[31:0]  <= mpu_cmd_data[31:0];
                                  wr_cnt       <= wr_cnt  +1;
                                 dp_wr_u1_enb <= 1;
                                
                                end
                               else 
                                  begin
                                  dp_wr_u1_enb <= 0;
                                  end 
                                
                              if ((blk_cnt ==8'd90 ) | mpu_cmd_grant | de_dly_flag  )
                              deint_cmd_req   <= 1'b0;
                              else  
                              deint_cmd_req   <= 1'b1;  
                              
                              if ( mpu_cmd_grant)
                             begin
                              blk_cnt    <= blk_cnt + 1;
                                 
                             end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[8:0]    <= deint_cmd_addr[8:0] + 4;
                            end    
                           if ( wr_cnt == 10'd360)
                              begin
                               de_dly_flag  <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt    <= 0;
                               dpr_wr_u1_addr <=  0;
                               
                              
                              end
                           if ( u_rd_cnt == 9'd360 )
                              begin
                              
                              de_dly1_flag    <= de_dly_flag;
                              
                             
                              
                              end  
                              
                            if ( de_dly1_flag )
                              
                                    begin
                                     de_write_st  <= de_v_write1;
                                    
                                     deint_cmd_addr[9] <= 1'b1;
                                     deint_cmd_addr[8:0]   <= 0;
                                     de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                                     
                                    end
                              
                                
                             
              
                           end
                           
               de_v_write0:  begin
                              if ( mpu_cmd_vld ) 
                                begin
                                  dpr_wr_v0_addr  <= dpr_wr_v0_addr  +1;
                                  dpr_wr_v0_data[31:0]  <= mpu_cmd_data[31:0];
                                  wr_cnt       <= wr_cnt  +1;
                                  dp_wr_v0_enb <= 1;
                                
                                end
                               else 
                                  begin
                                  dp_wr_v0_enb <= 0;
                                  end 
                                
                                
                              if ((blk_cnt ==8'd90 ) | mpu_cmd_grant | de_dly_flag  )
                              deint_cmd_req   <= 1'b0;
                              else  
                              deint_cmd_req   <= 1'b1;  
                              
                              if ( mpu_cmd_grant)
                             begin
                              blk_cnt    <= blk_cnt + 1;
                                 
                             end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[8:0]    <= deint_cmd_addr[8:0] + 4;
                            end    
                           if ( wr_cnt == 10'd360)
                              begin
                               de_dly_flag  <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt    <= 0;
                               dpr_wr_v0_addr  <=  0;
     
               //                 if ( de_row_cnt == 7'd70 )
               //                         begin
               //                            deint_cmd_addr[18:0]  <= 0;
               //                            line_cnt    <= 0;
                //                        end
                //                else 
                //                         begin
                                           line_cnt    <= line_cnt + 1;
                                           deint_cmd_addr[17:10] <= line_cnt + 1; 
                                          deint_cmd_addr[9:0]   <= 0;
                                           deint_cmd_addr[18]    <= 0;//read luma
                                         
                 //                        end   
                               
                              end
                            if ( de_row_cnt == 7'd0 )
                                begin
                                  if ( de_dly_flag )
                                    begin
                                     de_write_st  <= de_idle;
                                     de_dly_flag   <= 1'b0;
                                   
                                      de_row_cnt    <= de_row_cnt +1;
                                      
                                    end
                                end    
                            else
                            begin
                             if ( v_rd_cnt == 9'd360 )
                              begin
                              
                              de_dly1_flag    <= de_dly_flag;
                              
                             
                              
                              end  
                               if ( de_dly1_flag )
                              
                                    begin
                                     de_write_st  <= de_idle;
                                     de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                                     de_row_cnt    <= de_row_cnt +1;
                                    
                                     
                                    end
                              end      
                                
                   
                        end        
                de_v_write1:  begin
                              if ( mpu_cmd_vld ) 
                                begin
                                  dpr_wr_v1_addr  <= dpr_wr_v1_addr  +1;
                                  dpr_wr_v1_data[31:0]  <= mpu_cmd_data[31:0];
                                  wr_cnt       <= wr_cnt  +1;
                                  dp_wr_v1_enb <= 1;
                                
                                end
                               else 
                                  begin
                                  dp_wr_v1_enb <= 0;
                                  end 
                                
                                
                              if ((blk_cnt ==8'd90 ) | mpu_cmd_grant | de_dly_flag   )
                              deint_cmd_req   <= 1'b0;
                              else  
                              deint_cmd_req   <= 1'b1;  
                              
                              if ( mpu_cmd_grant)
                             begin
                              blk_cnt    <= blk_cnt + 1;
                                 
                             end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[8:0]    <= deint_cmd_addr[8:0] + 4;
                            end    
                           if ( wr_cnt == 10'd360)
                              begin
                              de_dly_flag   <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt[9:0]    <= 0;
                               dpr_wr_v1_addr  <=  0;
                               
                              
                     //          if ( de_row_cnt == 7'd70 )
                     //                   begin
                      //                     deint_cmd_addr[18:0]  <= 0;
                     //                      line_cnt    <= 0;
                     //                   end
                     //                 else 
                      //                   begin
                                           line_cnt    <= line_cnt + 1;
                                           deint_cmd_addr[17:10] <= line_cnt + 1; 
                                           deint_cmd_addr[9:0]   <= 0;
                                           deint_cmd_addr[18]    <= 0;//read luma
                                         
                         //                end   
                               
                               
                              end
                            if ( v_rd_cnt == 10'd360 )
                              begin
                              
                              de_dly1_flag    <= de_dly_flag;
                              
                             
                              
                              end  
                           if ( de_dly1_flag )
                              
                                    begin
                                     de_write_st  <= de_idle;
                                     de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                                     de_row_cnt    <= de_row_cnt +1;
                                     
                                   
                                    end
                               
                               
                   
                        end                      
                                       
                 endcase        
            
           end
        else
           begin
           de_write_st  <= 0;
           
           end   
                  
        end
        
  //  reg[12:0]   odd1_mid_t;
        
        
   always @( posedge sys_clk  )
       begin
           if (  sys_rstn == 1'b0 )
            begin
             
             odd0_up_t[12:0]    <= 0;
             odd0_down_t[12:0]  <= 0;
             odd1_up_t[12:0]    <= 0;
         //    odd1_mid_t[12:0]    <= 0;
             odd1_down_t[12:0]  <= 0;
             odd2_up_t[12:0]    <= 0;
             odd2_down_t[12:0]  <= 0;
             odd3_up_t[12:0]    <= 0;
             odd3_down_t[12:0]  <= 0;
             odd4_up_t[12:0]    <= 0;
             odd4_down_t[12:0]  <= 0;
             odd5_up_t[12:0]    <= 0;
             odd5_down_t[12:0]  <= 0;
             odd6_up_t[12:0]    <= 0;
             odd6_down_t[12:0]  <= 0;

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