de_inter.v

deinterlace的核心verilog

                 	          if ( de_row_cnt[0]==1'b0) 
                 	           begin
                 	          de_write_st <= de_luma_write0;
                 	           end
                 	          else
                 	           begin
                 	             de_write_st <= de_luma_write1;
                 	           end 
                 	           end 
                 	          else
                 	              begin
                 	                de_write_st <= de_wait;
                 	              end  
                 	         end          
                 de_luma_write0:
                           begin 
                            if ( mpu_cmd_vld ) 
                               
                                begin
                                  dpr_wr_lu0_addr  <= dpr_wr_lu0_addr +1;
                                  dpr_wr_lu0_data[15:0]  <= mpu_cmd_data[31:16];
                                  dpr_wr_lu1_addr  <= dpr_wr_lu1_addr +1;
                                  dpr_wr_lu1_data[15:0]  <= mpu_cmd_data[15:0];
                                  wr_cnt       <= wr_cnt  +1;
                                  dp_wr_lu0_enb <= 1;
                                  dp_wr_lu1_enb <= 1;
                                  if ( de_row_cnt[6:0] < 7'd70 )
                                    begin
                                      if ( a0_cnt[1:0] == 2'd0)
                                       begin
                                       dpr_wr_lu4_addr  <= dpr_wr_lu4_addr +1;
                                       dpr_wr_lu4_data[7:0]  <= mpu_cmd_data[7:0];
                                       
                                       end
                                       else if (a0_cnt[1:0] == 2'd1)
                                         begin
                                          dpr_wr_lu5_addr  <= dpr_wr_lu5_addr +1;
                                          dpr_wr_lu5_data[7:0]  <= mpu_cmd_data[7:0];
                                         end
                                       else 
                                           begin
                                          dpr_wr_lu6_addr  <= dpr_wr_lu6_addr +1;
                                          dpr_wr_lu6_data[7:0]  <= mpu_cmd_data[7:0];
                                           end
                                    end
                                  
                                end  
                              else
                                begin
                                  dp_wr_lu0_enb <= 0;
                                  dp_wr_lu1_enb <= 0;
                                end  
                                   
                           if ((blk_cnt ==8'd180 ) | mpu_cmd_grant | de_dly_flag  )
                              deint_cmd_req   <= 1'b0;
                           else  
                              deint_cmd_req   <= 1'b1;  
                            
                           if ( mpu_cmd_grant)
                             begin
                              blk_cnt    <= blk_cnt + 1;
                                 
                             end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[9:0]    <= deint_cmd_addr[9:0] + 4;
                            end
                           if ( wr_cnt == 10'd720)
                              begin
                    //           de_write_st  <= de_u_write0;
                               de_dly_flag   <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt    <= 0;
                               dpr_wr_lu0_addr  <=  0;
                               dpr_wr_lu1_addr  <=  0;
                               dpr_wr_lu4_addr  <=  0;
                               dpr_wr_lu5_addr  <=  0;
                               dpr_wr_lu6_addr  <=  0;
                               deint_cmd_addr[18]    <= 1;
                               deint_cmd_addr[9:0]   <= 0;
                                     deint_cmd_addr[17]    <= 0;
                                     deint_cmd_addr[16:10] <= line_cnt[7:1];
                                     
                                
                              
                              end
                              
                              
                          
                           if ( plk_wr_cnt == 10'd720 )
                              begin
                              
                              de_dly1_flag    <= de_dly_flag;
                              
                             
                              
                              end   
                              
                           if ( de_dly1_flag )
                               
                                  begin
                                  
                                     if( de_row_cnt[1:0] == 2'b00 )
                                     de_write_st  <= de_u_write0;
                                     else if ( de_row_cnt[1:0] == 2'b10)
                                       begin
                                      de_write_st <= de_u_write1;
                                       end
                                      
                                     de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                                     if ( a0_cnt == 2'b10 )
                                       begin
                                         a0_cnt  <= 0;
                                         
                                       end
                                      else 
                                         begin
                                           a0_cnt <= a0_cnt + 1;
                                         end
                                     
                                     
                                    end
                               
                                      
                            
                              
                           end 
                 de_luma_write1:  begin 
                            if ( mpu_cmd_vld ) 
                               
                                begin
                                  dpr_wr_lu2_addr  <= dpr_wr_lu2_addr  +1;
                                  dpr_wr_lu2_data[15:0]  <= mpu_cmd_data[31:16];
                                  dpr_wr_lu3_addr  <= dpr_wr_lu3_addr  +1;
                                  dpr_wr_lu3_data[15:0]  <= mpu_cmd_data[15:0];
                                   dp_wr_lu2_enb <= 1;
                                  dp_wr_lu3_enb <= 1;
                                  wr_cnt       <= wr_cnt  +1;
                                 if ( de_row_cnt[6:0] < 7'd70 )
                                    begin
                                      if ( a0_cnt[1:0] == 2'd0)
                                       begin
                                       dpr_wr_lu4_addr  <= dpr_wr_lu4_addr +1;
                                       dpr_wr_lu4_data[7:0]  <= mpu_cmd_data[7:0];
                                       end
                                       else if (a0_cnt[1:0] == 2'd1)
                                         begin
                                          dpr_wr_lu5_addr  <= dpr_wr_lu5_addr +1;
                                          dpr_wr_lu5_data[7:0]  <= mpu_cmd_data[7:0];
                                         end
                                       else 
                                           begin
                                          dpr_wr_lu6_addr  <= dpr_wr_lu6_addr +1;
                                          dpr_wr_lu6_data[7:0]  <= mpu_cmd_data[7:0];
                                           end
                                    end
                                end  
                                else
                                begin
                                  dp_wr_lu2_enb <= 0;
                                  dp_wr_lu3_enb <= 0;
                                end  
                                   
                           if ((blk_cnt ==8'd180 ) | mpu_cmd_grant | de_dly_flag )
                              deint_cmd_req   <= 1'b0;
                           else  
                              deint_cmd_req   <= 1'b1;  
                            
                           if ( mpu_cmd_grant)
                             begin
                              blk_cnt    <= blk_cnt + 1;
                                 
                             end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[9:0]    <= deint_cmd_addr[9:0] + 4;
                            end
                           if ( wr_cnt == 10'd720)
                              begin
                               de_dly_flag   <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt    <= 0;
                               dpr_wr_lu2_addr  <=  0;
                               dpr_wr_lu3_addr  <=  0;
                               dpr_wr_lu4_addr  <=  0;
                               dpr_wr_lu5_addr  <=  0;
                               dpr_wr_lu6_addr  <=  0;
                                
                                     if ( de_row_cnt == 7'd71 )
                                        begin
                                           deint_cmd_addr[18:0]  <= 0;
                                           line_cnt    <= 0;
                                        end
                               
                                line_cnt    <= line_cnt + 1;
                                      deint_cmd_addr[17:10] <= line_cnt + 1; 
                                      deint_cmd_addr[9:0]   <= 0;
                                      deint_cmd_addr[18]    <= 0;//read luma
                              end
                              
                            if ( plk_wr_cnt == 10'd720 )
                              begin
                              
                              de_dly1_flag    <= de_dly_flag;
                              
                             
                              
                              end     
                             
                           if ( de_dly1_flag )
                              
                                    begin
                                    
                                     de_write_st  <= de_idle;
                                     
                                      
                                    de_dly_flag   <= 1'b0;
                                     de_dly1_flag  <= 1'b0;
                                     
                                     de_row_cnt         <= de_row_cnt  + 1;
                                     if ( a0_cnt == 2'b10 )
                                       begin
                                         a0_cnt  <= 0;
                                         
                                       end
                                      else 
                                         begin
                                           a0_cnt <= a0_cnt + 1;
                                         end
                                     
                                     
                                    end
                              
                                     
                              
                           end  
              de_u_write0:  begin
                              if ( mpu_cmd_vld ) 
                               
                                begin
                                  dpr_wr_u0_addr  <= dpr_wr_u0_addr  +1;
                                  dpr_wr_u0_data[31:0]  <= mpu_cmd_data[31:0];
                                  wr_cnt       <= wr_cnt  +1;
                                   dp_wr_u0_enb <= 1;
                                
                                end
                               else 
                                  begin
                                  dp_wr_u0_enb <= 0;
                                  end 
                                
                              if ((blk_cnt ==8'd90 ) | mpu_cmd_grant | de_dly_flag   )
                              deint_cmd_req   <= 1'b0;
                              else  
                              deint_cmd_req   <= 1'b1;  
                              
                              if ( mpu_cmd_grant)
                               begin
                                blk_cnt    <= blk_cnt + 1;
                                 
                               end     
                           if(deint_cmd_enb)
                            begin
                            deint_cmd_addr[8:0]    <= deint_cmd_addr[8:0] + 4;
                            end    
                           if ( wr_cnt == 10'd360)
                              begin
                              de_dly_flag  <= 1'b1;
                               blk_cnt  <= 0;
                               wr_cnt    <= 0;
                               dpr_wr_u0_addr  <=  0;
                                                           
                              end
                              
                              if ( de_row_cnt == 0 )
                                begin
                                  if ( de_dly_flag )
                                    begin
                                    de_write_st  <= de_v_write0;
                                     
                                     deint_cmd_addr[9] <= 1'b1;
                                     deint_cmd_addr[8:0]   <= 0;
                                     de_dly_flag   <= 1'b0;