de_inter.v

deinterlace的核心verilog

          if ( sys_rstn == 1'b0 )
             begin
              de_row_flag[1:0]   <= 0;
             end
          else
             begin
                
               de_row_flag[1:0]  <= de_row_cnt[1:0];
             
             end   
         
         
         end
         
         reg   lowest_lu_enb_dly;
         reg   lowest_u_enb_dly;
         reg   lowest_v_enb_dly;
         reg   lowest_lu_enb_dly1;
         reg   lowest_u_enb_dly1;
         reg   lowest_v_enb_dly1;
         reg   lowest_lu_enb_dly2;
          reg   lowest_u_enb_dly2; 
          reg   lowest_v_enb_dly2; 
          reg   lowest_lu_enb_dly3;
          reg   lowest_u_enb_dly3;
          reg   lowest_v_enb_dly3; 
         
     always @ ( posedge sys_clk  )
       begin
         if ( sys_rstn == 1'b0 )
             begin
              lowest_lu_enb1   <= 0;
              lowest_u_enb    <= 0;
              lowest_v_enb    <= 0;
            
               lowest_lu_enb_dly1   <= 0;
              lowest_u_enb_dly1    <= 0;
              lowest_v_enb_dly1    <= 0;
               lowest_lu_enb_dly2   <= 0;
              lowest_u_enb_dly2    <= 0;
            
              lowest_v_enb_dly2    <= 0;
             
               lowest_lu_enb_dly3   <= 0;
              lowest_u_enb_dly3    <= 0;
              lowest_v_enb_dly3    <= 0;
               
             end
          
         else
             begin
              if ( (lowest_lu_enb1 == 1'b1 && plk_rd_cnt == 10'd720))
                begin
                     lowest_lu_enb1  <= 1'b0;
                  
                     lowest_lu_enb_dly1 <= 0;
                     lowest_lu_enb_dly2 <= 0;
                     lowest_lu_enb_dly3 <= 0;
                       
                end
             else if ((lowest_u_enb == 1'b1 &&  u_rd_cnt == 9'd360))
                begin
                     lowest_u_enb  <= 1'b0;
                     
                     lowest_u_enb_dly1 <= 0;
                     lowest_u_enb_dly2 <= 0;
                     lowest_u_enb_dly3 <= 0;
                end 
              else if ((lowest_v_enb == 1'b1 &&  v_rd_cnt == 9'd360))
                begin
                     lowest_v_enb  <= 1'b0;
                   
                     lowest_v_enb_dly1 <= 0;
                     lowest_v_enb_dly2 <= 0;
                     lowest_v_enb_dly3 <= 0;
                end     
              else
               begin  
              lowest_lu_enb_dly1  <= lowest_lu_enb_dly;
              lowest_u_enb_dly1  <= lowest_u_enb_dly;
              lowest_v_enb_dly1  <= lowest_v_enb_dly;
               lowest_lu_enb_dly2  <= lowest_lu_enb_dly1;
              lowest_u_enb_dly2  <= lowest_u_enb_dly1;
              lowest_v_enb_dly2  <= lowest_v_enb_dly1;
              lowest_lu_enb_dly3  <= lowest_lu_enb_dly2;
              lowest_u_enb_dly3  <= lowest_u_enb_dly2;
              lowest_v_enb_dly3  <= lowest_v_enb_dly2;
              lowest_lu_enb1   <= lowest_lu_enb_dly3;
              lowest_u_enb   <= lowest_u_enb_dly3;
              lowest_v_enb   <= lowest_v_enb_dly3;
              end
          end   
        
   
       end    
    
      
      
     always @ ( posedge sys_clk )
           begin
             if ( sys_rstn == 1'b0 )
               begin
                
                 
                 de_luma_vld_temp  <= 0;
                 de_u_vld_temp  <= 0;
                 de_v_vld_temp  <= 0;
                 de_luma_temp_vld   <= 0;
                 de_luma_dly       <= 0;
                 de_u_dly       <= 0;
                 de_v_dly       <= 0;
                 de_luma_dly1       <= 0;
                 de_u_dly1       <= 0;
                 de_v_dly1       <= 0;
                 de_luma_dly2       <= 0;
                 de_u_dly2     <= 0;
                 de_v_dly2       <= 0;
                  de_luma_dly3       <= 0;
                 de_u_dly3     <= 0;
                 de_v_dly3       <= 0;
                  de_luma_dly4       <= 0;
                 de_u_dly4     <= 0;
                 de_v_dly4       <= 0;
                 de_luma_vld_temp_plk  <= 0;
                 de_luma_vld_temp_plk_dly  <= 0;
                 
               
               end
              else if (  ( de_write_st == de_luma_write0 | de_write_st == de_luma_write1) && de_start)
                     begin
                            
                            de_luma_dly         <= mpu_cmd_vld;
                             de_luma_dly1         <= de_luma_dly;
                             de_luma_dly2         <= de_luma_dly1;
                            
                              de_luma_dly3         <= de_luma_dly2;
                              de_luma_dly4         <= de_luma_dly3;
                            de_luma_temp_vld    <=  de_luma_dly3;
                            de_luma_vld_temp         <= de_luma_temp_vld;
                            de_luma_vld_temp_plk     <= de_luma_vld_temp;
                            de_luma_vld_temp_plk_dly     <= de_luma_vld_temp_plk;
                     end
              else if ( (de_write_st == de_u_write0 | de_write_st == de_u_write1 ) && de_start )
                     begin
                            de_u_dly      <= mpu_cmd_vld;
                            
                            de_u_dly1      <= de_u_dly;
                            de_u_dly2      <= de_u_dly1;
                           de_u_dly3      <= de_u_dly2;
                           de_u_dly4      <= de_u_dly3;
                            de_u_vld_temp       <= de_u_dly4;             
                       
                     end
              else  if ( (de_write_st == de_v_write0 | de_write_st == de_v_write1 ) && de_start )
                     begin
                            de_v_dly       <= mpu_cmd_vld;
                            de_v_dly1       <= de_v_dly;
                            de_v_dly2      <= de_v_dly1;
                            de_v_dly3      <= de_v_dly2;
                             de_v_dly4      <= de_v_dly3;
                            de_v_vld_temp       <= de_v_dly4;              
                       
                     end    
              else
                    begin
                      de_luma_vld_temp     <= 0;
                      de_u_vld_temp        <= 0;
                      de_v_vld_temp        <= 0;
                      de_luma_temp_vld  <= 0;
                      de_luma_dly       <= 0;
                      de_u_dly       <= 0;
                      de_v_dly       <= 0;
                     de_luma_dly1       <= 0;
                     de_u_dly1       <= 0;
                     de_v_dly1       <= 0;
                      de_luma_dly2       <= 0;
                    de_u_dly2     <= 0;
                      de_v_dly2       <= 0;
                      de_luma_dly3       <= 0;
                    de_u_dly3     <= 0;
                      de_v_dly3       <= 0;
                      de_luma_vld_temp_plk  <= 0;
                      de_luma_dly4       <= 0;
                     de_u_dly4     <= 0;
                     de_v_dly4       <= 0;
                     de_luma_vld_temp_plk_dly   <= 0;
                    
                    end          
                   
           
           end   
           
         
        
          
        always @ ( posedge sys_clk )
         begin
          if ( sys_rstn == 1'b0 )
             begin
             de_luma_vld_plk  <= 0;
             end_pot_lu_enb1  <= 0;
             de_out_luma_enb  <= 0;
             lowest_lu_enb   <= 0;
              odd_play_end    <= 0;
             end
          else
             begin
                 de_luma_vld_plk  <= de_luma_vld_temp_plk_dly;
                 end_pot_lu_enb1  <= end_pot_lu_enb; 
                 de_out_luma_enb  <=  de_out_luma_enb_t;
                 lowest_lu_enb  <= lowest_lu_enb1;
                 odd_play_end    <= odd_play_end_t;
             end   
         
         
         end  
             
    
      reg[1:0]   a0_cnt;
         
   always @(posedge sys_clk  )
        begin
         if ( sys_rstn==1'b0 )
           begin
   

            de_row_cnt        <= 0;
            de_write_st       <= 0;
            dpr_wr_lu0_addr[9:0] <= 0;
            dpr_wr_lu1_addr[9:0] <= 0;
            dpr_wr_lu2_addr[9:0] <= 0;
            dpr_wr_lu3_addr[9:0] <= 0;
            dpr_wr_lu4_addr[9:0] <= 0;
            dpr_wr_lu0_data[15:0]   <= 0;
            dpr_wr_lu1_data[15:0]   <= 0;
            dpr_wr_lu2_data[15:0]   <= 0;
            dpr_wr_lu3_data[15:0]   <= 0;
            dpr_wr_lu4_data[7:0]   <= 0;
            dpr_wr_lu5_data[7:0]   <= 0;
            dpr_wr_lu6_data[7:0]   <= 0;
            
            
            dpr_wr_u0_addr[8:0]      <= 0;
            dpr_wr_u1_addr[8:0]      <= 0;
            dpr_wr_v0_addr[8:0]      <= 0;
            dpr_wr_v1_addr[8:0]      <= 0;
            dpr_wr_u0_data[31:0]     <= 0;
            dpr_wr_u1_data[31:0]     <= 0;
            dpr_wr_v0_data[31:0]     <= 0;
            dpr_wr_v1_data[31:0]     <= 0;
            
            de_dly_flag       <= 0;
            de_dly1_flag      <= 0;
     //       de_dly2_flag       <= 0;
     //       de_dly3_flag      <= 0;
            
            deint_cmd_req    <= 0;
            deint_cmd_addr   <= 0;
            blk_cnt          <= 0;
            wr_cnt           <= 0;
             line_cnt            <= 0;
             a0_cnt     <= 0;
             dp_wr_lu0_enb <= 0;
             dp_wr_lu1_enb <= 0;
             dp_wr_lu2_enb <= 0;
             dp_wr_lu3_enb <= 0;
             dp_wr_u0_enb <= 0;
             dp_wr_u1_enb <= 0;
             dp_wr_v0_enb <= 0;
             dp_wr_v1_enb <= 0;
            
            
           end
           
         else
           if (    de_start  )
            begin
            
               case( de_write_st )
                 de_idle: begin
                            de_write_st <= de_wait ;
                           
                          end  
                 de_wait:  begin
                             if ( rd_buf_flag_d != rd_buf_flag )
                              begin