de_inter.v

deinterlace的核心verilog

  module  de_inter (
   
       sys_clk,
       sys_rstn,
       mpu_cmd_grant,
       mpu_cmd_data,
       mpu_cmd_vld,
       
       deint_cmd_req,
       deint_cmd_enb,
       deint_cmd_addr,
     
       de_out_lu_data,
       de_out_u_data,
       de_out_v_data,
       
       de_start,
       de_luma_vld,
       de_u_vld,
       de_v_vld,
       de_row_flag,
       odd_play_end,
       de_out_luma_enb,
       de_out_u_enb,
       de_out_v_enb,
       lowest_lu_enb,
       lowest_u_enb,
       lowest_v_enb,
       rd_buf_flag,
       rd_buf_flag_d
    
   );
        
         input        sys_clk;
         input        sys_rstn;
         input        de_start;
         
         input        mpu_cmd_grant;
         input[31:0]  mpu_cmd_data;
         input        mpu_cmd_vld;
         
         input        rd_buf_flag;
         input        rd_buf_flag_d;
         
         output      deint_cmd_req;
         output      deint_cmd_enb;
         output      deint_cmd_addr;
      //   output[1:0] deint_cmd_len;
      //   output      deint_cmd_rwn;
         
         reg        deint_cmd_req;
         reg        deint_cmd_enb;
         reg[22:0]        deint_cmd_addr;
         
         
         
         output[31:0]  de_out_lu_data;
         output[31:0]  de_out_u_data;
         output[31:0]  de_out_v_data;
         
         output        de_luma_vld;
         output        de_u_vld;
         output        de_v_vld;
         output        odd_play_end;
         
         output[1:0]  de_row_flag;
         
         output       de_out_luma_enb;
         output       de_out_u_enb;
         output       de_out_v_enb;
         
         output       lowest_lu_enb;
         output       lowest_u_enb;
         output       lowest_v_enb;
         
         reg       de_out_luma_enb_t;
         reg       de_out_luma_enb;
         reg       de_out_u_enb;
         reg       de_out_v_enb;
         
         reg       lowest_lu_enb;
         reg       lowest_lu_enb1;
         reg       lowest_u_enb;
         reg       lowest_v_enb;
         
         wire     dpram_enb;
         
         assign   dpram_enb = 1'b1;
         
         wire     de_luma_vld;
         wire     de_u_vld;
         wire     de_v_vld;
         
          reg[9:0]      plk_wr_cnt; 
         reg[2:0]    de_write_st;
                  
         reg          de_luma_vld_temp;
         reg          de_u_vld_temp;
         reg          de_v_vld_temp;
         
         reg[31:0]    de_out_lu_data_t;
         reg[31:0]    de_out_lu_data;
         reg[31:0]    de_out_u_data;
         reg[31:0]    de_out_v_data;
         
         
         parameter   de_idle = 3'd0,
                     de_wait = 3'd1,
                     de_luma_write0 = 3'd2,
                     de_luma_write1 = 3'd3,
                     de_u_write0  = 3'd4,
                     de_u_write1  = 3'd5,
                     de_v_write0  = 3'd6,
                     de_v_write1  = 3'd7;
       
    //     reg [1:0]   st_flag;
    //     parameter   st_luma_flag  = 2'd0,
    //                 st_u_flag  = 2'd1,
    //                 st_v_flag  = 2'd2;
     
                  
         reg [7:0]  blk_cnt;
         reg[9:0]   wr_cnt;
         reg[9:0]   rd_cnt;
         reg[8:0]   u_rd_cnt;
         reg[8:0]   v_rd_cnt;
         reg[9:0]   plk_rd_cnt;
         reg[7:0]   line_cnt;
       
            
         reg[6:0]   de_row_cnt;
         reg[9:0]   dpr_wr_lu0_addr;
         reg[9:0]   dpr_wr_lu1_addr;
         reg[9:0]   dpr_wr_lu2_addr;
         reg[9:0]   dpr_wr_lu3_addr;
         reg[9:0]   dpr_wr_lu4_addr;
         reg[9:0]   dpr_wr_lu5_addr;
         reg[9:0]   dpr_wr_lu6_addr;
         
         reg[9:0]   dpr_rd_lu0_addr;
         reg[9:0]   dpr_rd_lu1_addr;
         reg[9:0]   dpr_rd_lu2_addr;
         reg[9:0]   dpr_rd_lu3_addr;
         reg[9:0]   dpr_rd_lu4_addr;
         reg[9:0]   dpr_rd_lu5_addr;
         reg[9:0]   dpr_rd_lu6_addr;
         
         reg[15:0]  dpr_wr_lu0_data;
         reg[15:0]  dpr_wr_lu1_data;
         reg[15:0]  dpr_wr_lu2_data;
         reg[15:0]  dpr_wr_lu3_data;
         reg[7:0]   dpr_wr_lu4_data;
         reg[7:0]   dpr_wr_lu5_data;
         reg[7:0]   dpr_wr_lu6_data;
         
         reg[31:0]     dpr_wr_u0_data;
         reg[31:0]     dpr_wr_u1_data;
         reg[31:0]     dpr_wr_v0_data;
         reg[31:0]     dpr_wr_v1_data;
         
         reg[8:0]       dpr_wr_u0_addr;
         reg[8:0]       dpr_wr_u1_addr;
         reg[8:0]       dpr_wr_v0_addr;
         reg[8:0]       dpr_wr_v1_addr;
         
         reg[8:0]       dpr_rd_u0_addr;
         reg[8:0]       dpr_rd_u1_addr;
         reg[8:0]       dpr_rd_v0_addr;
         reg[8:0]       dpr_rd_v1_addr;
         
        
         
         wire[15:0]   lu0;
         wire[15:0]   lu1;
         wire[15:0]   lu2;
         wire[15:0]   lu3;
         wire[7:0]    lu4;
         wire[7:0]    lu5;
         wire[7:0]    lu6;
             
         
         wire[31:0]    u_out0;
         wire[31:0]    u_out1;
         wire[31:0]    v_out0;
         wire[31:0]    v_out1;
         reg         odd_play_end;
         reg         odd_play_end_t;
         
         
         reg        de_dly_flag;
         reg        de_dly1_flag;
         
      
         reg[1:0]  de_row_flag; 
         
     //    reg        de_luma_dly1;
     //    reg         de_u_dly1;
     //    reg         de_v_dly1;
         
         reg[12:0]   odd0_up_t;
         reg[12:0]   odd0_down_t;
         reg[12:0]   odd1_up_t;
         reg[12:0]   odd1_down_t;
         reg[12:0]   odd2_up_t;
         reg[12:0]   odd2_down_t;
         reg[12:0]   odd3_up_t;
         reg[12:0]   odd3_down_t;
         reg[12:0]   odd4_up_t;
         reg[12:0]   odd4_down_t;
         reg[12:0]   odd5_up_t;
         reg[12:0]   odd5_down_t;
         reg[12:0]   odd6_up_t;
         reg[12:0]   odd6_down_t;
         
         reg        dp_wr_lu0_enb;
         reg        dp_wr_lu1_enb;
         reg        dp_wr_lu2_enb;
         reg        dp_wr_lu3_enb;
         reg        dp_wr_v0_enb;
         reg        dp_wr_v1_enb;
         reg        dp_wr_u0_enb;
         reg        dp_wr_u1_enb;
         reg  de_luma_temp_vld;
       reg  de_luma_dly;
       reg  de_u_dly;
       reg  de_v_dly;
       reg  de_luma_dly1;
       reg  de_u_dly1;
       reg  de_v_dly1;
       reg  de_luma_dly2;
       reg  de_u_dly2;
       reg  de_v_dly2;
       reg  de_luma_dly3;
       reg  de_u_dly3;
       reg  de_v_dly3;
       reg  de_luma_dly4;
       reg  de_u_dly4;
       reg  de_v_dly4;
       reg  de_luma_vld_temp_plk;
       reg  de_luma_vld_temp_plk_dly;
         reg[7:0]     de_out_data_plk0;
        reg[15:0]     de_out_data_plk1;
        reg[15:0]     de_out_data_plk2;
        wire[7:0]     dpr_rd_data_plk0;
        wire[15:0]     dpr_rd_data_plk1;
        wire[15:0]     dpr_rd_data_plk2;
        reg[9:0]      dpr_wr_addr_plk0;
        reg[9:0]      dpr_wr_addr_plk1;
        reg[9:0]      dpr_wr_addr_plk2;
        reg[9:0]      dpr_rd_addr_plk0;
        reg[9:0]      dpr_rd_addr_plk1;
        reg[9:0]      dpr_rd_addr_plk2;
  
        reg            end_pot_lu_enb;
        reg            end_pot_u_enb;
        reg            end_pot_v_enb;
        reg            end_pot_lu_enb1;
        reg           de_luma_vld_plk;
         
      assign     de_luma_vld  =  de_luma_vld_plk | end_pot_lu_enb1;
      assign     de_u_vld  =  de_u_vld_temp | end_pot_u_enb;
      assign     de_v_vld  =  de_v_vld_temp | end_pot_v_enb;
         
         
        
    always @(posedge sys_clk)
    begin
        if(sys_rstn==1'b0)
        begin
   
            deint_cmd_enb <= 0;
            
            
            
        end
        else
        begin
            deint_cmd_enb <= mpu_cmd_grant;
            
   
       end
    end 
         
     always @ ( posedge sys_clk )
         begin