init_statemachine.vhd

xilinx ddr3最新VHDL代码,通过调试

constant EMR_OPMODE     : std_logic_vector(0 to (C_DDR_AWIDTH-3)-1) :=  
                                (others => '0');

constant RST_DLL_REGDATA    : std_logic_vector(0 to C_DDR_AWIDTH-1) :=
                    RSTDLL_OPMODE & CAS_LAT & BRST_TYPE & BRST_LEN;
constant EN_DLL_REGDATA     : std_logic_vector(0 to C_DDR_AWIDTH-1) :=
                    (others => '0');
constant NORM_OP_REGDATA    : std_logic_vector(0 to C_DDR_AWIDTH-1) :=
                    NORM_OPMODE & CAS_LAT & BRST_TYPE & BRST_LEN;

-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
type INIT_STATE_TYPE is (RESET, PRECHARGE1, ENABLE_DLL, RESET_DLL, PRECHARGE2, 
                         REFRESH1, REFRESH2, SET_OP, DONE);
signal initsm_ns        : INIT_STATE_TYPE;
signal initsm_cs        : INIT_STATE_TYPE;

-- combinational versions of registered outputs
signal precharge_cmb            : std_logic;
signal load_mr_cmb              : std_logic;
signal tpwrup_load_cmb          : std_logic;
signal refresh_cmb              : std_logic;
signal register_data_cmb        : std_logic_vector(0 to C_DDR_AWIDTH-1);
signal register_sel_cmb         : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
signal init_done_cmb            : std_logic;
signal ddr_cke_cmb              : std_logic_vector(0 to C_NUM_BANKS_MEM-1);

-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------

 
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------

begin  -- architecture imp

--------------------------------------------------------------------------------
-- Initialization State Machine
-- INITSM_CMB:     combinational process for determining next state
-- INITSM_REG:     state machine registers
--------------------------------------------------------------------------------
    -- Combinational process
INITSM_CMB: process (Trefi_pwrup_end, Cmd_done, initsm_cs)
begin
-- Set default values
precharge_cmb <= '0';
load_mr_cmb <= '0';
tpwrup_load_cmb <= '0';
refresh_cmb <= '0';       
register_data_cmb <= (others => '0');
register_sel_cmb <= (others => '0'); 
init_done_cmb <= '0';
ddr_cke_cmb <= (others => '1');
initsm_ns <= initsm_cs;

case initsm_cs is
-------------------------- RESET --------------------------
    when RESET =>
        -- reset state
        -- the register process will keep initsm_cs in IDLE
        -- when reset is released, the 200us counter will start
        -- when this counter finishes, move to the PRECHARGE1 state
        ddr_cke_cmb <= (others => '0');
        if Trefi_pwrup_end = '1' then
            initsm_ns <= PRECHARGE1;
            precharge_cmb <= '1';
            ddr_cke_cmb <= (others => '1');
        end if;
        
-------------------------- PRECHARGE1 --------------------------
    when PRECHARGE1 =>
        -- wait for IDLE
        -- once IDLE asserts, prepare for ENABLE_DLL state
        -- select the Extended Mode Register and set the data
        if Cmd_done = '1' then
            initsm_ns <= ENABLE_DLL;
            register_sel_cmb <= EMR_SEL;
            register_data_cmb <= EN_DLL_REGDATA;
            load_mr_cmb <= '1';
        end if;        

-------------------------- ENABLE_DLL --------------------------
    when ENABLE_DLL =>
        -- wait for IDLE
        -- once IDLE asserts, prepare for RESET_DLL state
        -- select the Mode Register and set the data
        -- enable the 200 clock timer
        if Cmd_done = '1' then
            initsm_ns <= RESET_DLL;
            register_sel_cmb <= MR_SEL;
            register_data_cmb <= RST_DLL_REGDATA;
            tpwrup_load_cmb <= '1';
            load_mr_cmb <= '1';
        end if;
           
-------------------------- RESET_DLL --------------------------
    when RESET_DLL =>
        -- wait in this state for 200 clocks
        if Trefi_pwrup_end = '1' then
            -- prepare for PRECHARGE2 state
            initsm_ns <= PRECHARGE2;
            precharge_cmb <= '1';
        end if;
            
-------------------------- PRECHARGE2 --------------------------
    when PRECHARGE2 =>
        -- wait in this state for IDLE
        -- once IDLE asserts, prepare for REFRESH1 state
        if Cmd_done = '1' then
            initsm_ns <= REFRESH1;
            refresh_cmb <= '1';
        end if;
        
-------------------------- REFRESH1 --------------------------
    when REFRESH1 =>
        -- wait in this state for refresh period to end
        -- once cycle ends, prepare for REFRESH2 state
        if Cmd_done = '1' then
            initsm_ns <= REFRESH2;
            refresh_cmb <= '1';
        end if;
        
-------------------------- REFRESH2 --------------------------
    when REFRESH2 =>
        -- wait in this state for IDLE
        -- once IDLE asserts, prepare for SET_OP state
        -- select the Mode Register and set the data
        if Cmd_done = '1' then
            initsm_ns <= SET_OP;
            register_sel_cmb <= MR_SEL;
            register_data_cmb <= NORM_OP_REGDATA;
            load_mr_cmb <= '1';
        end if;

-------------------------- SET_OP --------------------------
    when SET_OP =>
        -- wait in this state for IDLE
        -- once IDLE asserts, prepare for DONE state
        if Cmd_done = '1' then
            initsm_ns <= DONE;
        end if;

---------------------------- DONE ----------------------------
    when DONE =>
        -- once in this state, initialization is done
        -- state machine stays in this state until a reset
        -- sets the current state to IDLE and the process starts again.
        initsm_ns <= DONE;
        init_done_cmb <= '1';

-------------------------- DEFAULT --------------------------
    when others => 
        initsm_ns <= RESET;
end case;
end process INITSM_CMB;
    
INITSM_REG: process (Clk)
begin

    if (Clk'event and Clk = '1') then
        if (Rst = RESET_ACTIVE) then
            initsm_cs <= RESET;
            Precharge <= '0';
            Load_mr <= '0';
            Refresh <= '0';
            Tpwrup_load <= '0';
            Register_data <= (others => '0');
            Register_sel <= (others => '0');
            Init_done <= '0';
            DDR_CKE <= (others => '0');
        else
            initsm_cs <= initsm_ns;
            Precharge <= precharge_cmb;
            Load_mr <= load_mr_cmb;
            Refresh <= refresh_cmb;
            Tpwrup_load <= tpwrup_load_cmb;
            Register_data <= register_data_cmb;
            Register_sel <= register_sel_cmb;
            Init_done <= init_done_cmb;
            DDR_CKE <= ddr_cke_cmb;
        end if;
    end if;
end process INITSM_REG;    


end imp;