📄 init_statemachine.vhd
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-------------------------------------------------------------------------------
-- $Id: init_statemachine.vhd,v 1.2 2004/04/07 20:44:51 jennj Exp $
-------------------------------------------------------------------------------
-- init_statemachine.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: init_statemachine.vhd
-- Version: v1.10a
-- Description: This state machine controls the power-up sequence of commands
-- to the DDR.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/07/02 First Version
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-- JLJ 04/06/04
-- ^^^^^^
-- Resized DDR_CKE to DDR_CKE (0:C_NUM_BANKS_MEM-1) for each bank of DDR
-- memory to have a dedicated CKE.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- supported number of memory banks
-- C_DDR_AWIDTH -- width of DDR address bus
-- C_DDR_BANK_AWIDTH -- width of DDR bank address bus
-- C_DDR_BRST_SIZE -- length of DDR burst
-- C_DDR_CAS_LAT -- DDR CAS latency
--
-- Definition of Ports:
-- -- inputs
-- Cmd_done -- indicates Command SM is in IDLE state
-- Trefi_pwrup_end -- indicates 200uS, 200clocks has passed
--
-- -- outputs
-- Precharge -- instructs Command SM to do a PRECHARGE command
-- Load_mr -- instructs Command SM to do a LOAD_MR command
-- Tpwrup_load -- loads the refresh_pwrup counter
-- Refresh -- instructs Command SM to do a Refresh command
-- Register_data -- data for the mode reg or extended mode reg
-- Register_sel -- selects the mode reg or extended mode reg
-- Init_done -- indicates initialization is complete
-- -- NOTE: This signal could be a top-level output
-- used as an interrupt to indicate init is done
-- DDR_CKE -- DDR clock enable(s)
--
-- -- Clocks and reset
-- Clk
-- Rst
---------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity init_statemachine is
generic ( C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_DDR_AWIDTH : integer;
C_DDR_BANK_AWIDTH : integer;
C_DDR_BRST_SIZE : integer;
C_DDR_CAS_LAT : integer);
port (
-- inputs
Cmd_done : in std_logic;
Trefi_pwrup_end : in std_logic;
-- outputs
Precharge : out std_logic;
Load_mr : out std_logic;
Tpwrup_load : out std_logic;
Refresh : out std_logic;
Register_data : out std_logic_vector(0 to C_DDR_AWIDTH-1);
Register_sel : out std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
Init_done : out std_logic;
DDR_CKE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
-- Clocks and reset
Clk : in std_logic;
Rst : in std_logic
);
end entity init_statemachine;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of init_statemachine is
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
-- Mode register definition
constant NUM_BRSTLEN_BITS : integer := 3;
constant NUM_BRSTTYPE_BITS : integer := 1;
constant NUM_CASLAT_BITS : integer := 3;
constant NUM_OPMODE_BITS : integer := C_DDR_AWIDTH - NUM_BRSTLEN_BITS
- NUM_BRSTTYPE_BITS
- NUM_CASLAT_BITS;
constant EMR_SEL : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1) :=
conv_std_logic_vector(1, C_DDR_BANK_AWIDTH);
constant MR_SEL : std_logic_vector(0 to C_DDR_BANK_AWIDTH-1) :=
(others => '0');
constant QFC_N : std_logic := '0'; -- QFC function disabled
constant EN_DLL : std_logic := '1'; -- enable DLL
constant DRIVE_STR : std_logic := '0'; -- normal drive strength
constant BRST_TYPE : std_logic := '0'; -- sequential burst type
constant BRST_LEN : std_logic_vector(0 to NUM_BRSTLEN_BITS-1) :=
conv_std_logic_vector(log2(C_DDR_BRST_SIZE), NUM_BRSTLEN_BITS);
constant CAS_LAT : std_logic_vector(0 to NUM_CASLAT_BITS-1) :=
conv_std_logic_vector(C_DDR_CAS_LAT, NUM_CASLAT_BITS);
constant NORM_OPMODE : std_logic_vector(0 to NUM_OPMODE_BITS-1) :=
(others => '0');
constant RSTDLL_OPMODE : std_logic_vector(0 to NUM_OPMODE_BITS-1) :=
conv_std_logic_vector(2, NUM_OPMODE_BITS);
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