📄 ddr_controller2.vhd
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-------------------------------------------------------------------------------
-- $Id: ddr_controller.vhd,v 1.8 2004/08/09 22:17:53 jennj Exp $
-------------------------------------------------------------------------------
-- ddr_controller.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ddr_controller.vhd
-- Version: v1.10a
-- Description: DDR controller with IPIC interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ddr_controller.vhd
-- -- read_data_path.vhd
-- -- data_statemachine.vhd
-- -- command_statemachine.vhd
-- -- init_statemachine.vhd
-- -- counters.vhd
-- -- io_registers.vhd
-- -- clock_gen.vhd
-- -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 05/02/02 First Version
-- ^^^^^^
-- First version of DDR controller
-- ~~~~~~
-- ALS 06/05/02
-- ^^^^^^
-- Replaced C_CLK_FREQ with C_CLK_PERIOD
-- ~~~~~~
-- ALS 06/07/02
-- ^^^^^^
-- Made modifications for FIFO implementation of read data path. Added
-- C_FAMILY generic.
-- ~~~~~~
-- ALS 07/12/02
-- ^^^^^^
-- Added C_REG_DIMM generic. When C_REG_DIMM=1, add a 1-clock pipeline
-- delay to write_data, write_data_mask, write_data_en, write_dqs_en.
-- Also, add 1 to the CAS_LATENCY to account for the register delay in
-- the DIMM. Changed generic C_INCLUDE_CLK90_GEN to C_INCLUDE_CLK90_DCM
-- and added generic C_INCLUDE_DDRCLK_DCM so that the inclusion of the
-- DDR clock DCM and the output registers to generate the DDR clock output
-- ~~~~~~
-- ALS 06/25/03
-- ^^^^^^
-- Version C:
-- Use latest IPIFs to remove latency and support indeterminate bursts
-- Add INIT_DONE as output pin
-- Provide C_SIM_INIT_TIME parameter to allow simulation to run faster
-- Remove XST workarounds
-- Assert TOUTSUP during transfers
-- ~~~~~~
-- JLJ 11/11/03
-- ^^^^^^
-- Version D:
-- Add support for ECC capability. Add ports and register logic for ECC
-- check bits. Include C_INCLUDE_ECC_SUPPORT parameter and NUM_ECC_BITS
-- constant on generic mapping. Seperate IP2Bus_AddrAck into
-- IP2Bus_RdAddrAck and IP2Bus_WrAddrAck.
-- ~~~~~~
-- JLJ 02/13/04
-- ^^^^^^
-- Add Bus2IP_CS as port on data_statemachine module.
-- ~~~~~~
-- JLJ 02/16/04
-- ^^^^^^
-- Removed C_PULLUPS generic. If this parameter was set to 1, the DDR DQS lines
-- had pullups. If this parameter was set to 0, then pulldowns were assumed. The
-- new default setting will assume pullups.
--
-- Added bursting optimizations. C_INCLUDE_BURSTS parameter is now used in
-- command_statemachine, data_statemachine, and ipic_if. Removed C_INCLUDE_BURSTS
-- parameter on generic map for read_data_path module.
-- ~~~~~~
-- JLJ 02/18/04
-- ^^^^^^
-- Add Sys_Clk_n, Clk90_in_n, and DDR_Clk90_in_n signals on port mapping for DDR core.
-- This update of the core requires global inversion on clock inputs to prevent any
-- duty cycle distortion as system frequencies increase.
-- ~~~~~~
-- JLJ 02/20/04
-- ^^^^^^
-- Add support for multiple memory banks with new parameter, C_NUM_BANKS_MEM.
-- Supported number of memory banks is 1 to 4. Create logic for DDR_CSn in
-- command_statemachine, but register output logic in IOB (in io_registers module).
-- ~~~~~~
-- JLJ 02/25/04
-- ^^^^^^
-- Create multiple DDR clock pairs to support clocking requirements
-- of certain DDR SDRAM DIMM vendors. Added support for up to 3 differential
-- DDR clock pairs. Renamed DDR_Clk and DDR_Clkn to DDR_Clk0 and DDR_Clk0n.
-- Added ports DDR_Clk1, DDR_Clk1n, DDR_Clk2, DDR_Clk2n. Added support for
-- 2 output DDR clock enables. Renamed DDR_CKE to DDR_CKE0, and added DDR_CKE1.
-- ~~~~~~
-- JLJ 03/18/04
-- ^^^^^^
-- Updated to version v1.10a. Added support for Virtex4 (uses family.vhd in
-- proc_common_v2_00_a). Also updated to proc_common_v2_00_a.
-- ~~~~~~
-- JLJ 04/06/04
-- ^^^^^^
-- Added parameter, C_NUM_CLK_PAIRS for the number of differential DDR clock
-- pairs needed in design. Renamed DDR_Clk0, DDR_Clk0n, DDR_Clk1, DDR_Clk1n,
-- DDR_Clk2, & DDR_Clk2n to DDR_Clk (0:C_NUM_CLK_PAIRS-1) and
-- DDR_Clkn (0:C_NUM_CLK_PAIRS-1).
--
-- Renamed DDR_CKE0 and DDR_CKE1 to DDR_CKE (0:C_NUM_BANKS_MEM-1). Each
-- bank of DDR memory will have a dedicated CKE.
-- ~~~~~~
-- JLJ 04/08/04
-- ^^^^^^
-- Modified data_statemachine module Bus2IP_Burst port mapping. New assignment
-- is burst signal from ipic_if module.
-- ~~~~~~
-- JLJ 05/05/04
-- ^^^^^^
-- Add component declaration for Virtex-4 primitives, IDDR & ODDR, in
-- io_registers and clock_gen modules.
-- ~~~~~~
-- JLJ 08/09/04
-- ^^^^^^
-- Remove component declaration for Virtex-4 primitives, IDDR & ODDR, in
-- io_registers and clock_gen modules.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.all;
library ddr_v1_10_a;
use ddr_v1_10_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_FAMILY -- target FPGA family
-- C_NUM_BANKS_MEM -- supported number of memory banks
-- C_NUM_CLK_PAIRS -- supported number of DDR clock pairs
-- C_REG_DIMM -- support registered ddr dimm
-- C_DDR_TMRD -- Load Mode Register command cycle time
-- C_DDR_TWR -- write recovery time
-- C_DDR_TRAS -- delay after ACTIVE command before
-- -- PRECHARGE command
-- C_DDR_TRC -- delay after ACTIVE command before
-- -- another ACTIVE or AUTOREFRESH command
-- C_DDR_TRFC -- delay after AUTOREFRESH before another command
-- C_DDR_TRCD -- delay after ACTIVE before READ/WRITE
-- C_DDR_TRRD -- delay after ACTIVE row a before ACTIVE
-- -- row b
-- C_DDR_TRP -- delay after PRECHARGE command
-- C_DDR_TREFC -- refresh to refresh command interval
-- C_DDR_TREFI -- average periodic refresh command interval
-- C_DDR_CAS_LAT -- Device CAS latency
-- C_DDR_DWIDTH -- DDR data width of each device
-- C_DDR_AWIDTH -- DDR row address width
-- C_DDR_COL_AWIDTH -- DDR column address width
-- C_DDR_BANK_AWIDTH -- DDR bank address width
-- C_DDR_BRST_SIZE -- DDR burst size
-- C_IPIF_DWIDTH -- IPIC data width
-- C_IPIF_AWIDTH -- IPIC address width
-- C_INCLUDE_BURSTS -- include support for bus burst transactions
-- C_CLK_PERIOD -- processor bus clock period
-- C_OPB_BUS -- processor bus is OPB
-- C_PLB_BUS -- processor bus is PLB
-- C_SIM_INIT_TIME_PS -- DDR initialization time to be used in simulation
-- C_INCLUDE_ECC_SUPPORT -- Include ECC support
-- NUM_ECC_BITS -- Number of ECC bits
--
-- Definition of Ports:
-- -- IPIC
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Data -- Processor data
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_RdReq -- Processor read request
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_Burst -- Processor burst
-- Bus2IP_IBurst -- Processor indeterminate burst
-- Bus2IP_CS -- DDR memory is being accessed
-- ECC_chk_bits_wr -- ECC check bits to write from ECC logic (when C_INCLUDE_ECC_SUPPORT=1)
-- ECC_chk_bits_rd -- ECC check bits read from memory (when C_INCLUDE_ECC_SUPPORT=1)
--
-- -- IPIC outputs
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_AddrAck -- Address phase acknowledge (inc address count)
-- IP2Bus_Busy -- IP busy (issue re-arbitrate during address phase)
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_Retry -- Retry indicator
-- IP2Bus_ToutSup -- Suppress watch dog timer
--
-- -- DDR interface signals
-- DDR_Clk -- DDR clock output(s)
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