ddr_cntl2_wrapper.vhd

xilinx ddr3最新VHDL代码,通过调试

-------------------------------------------------------------------------------
-- ddr_sdram_16mx16_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library proc_common_v2_00_a;
use proc_common_v2_00_a.all;

library interrupt_control_v1_00_a;
use interrupt_control_v1_00_a.all;

library wrpfifo_v1_01_b;
use wrpfifo_v1_01_b.all;

library rdpfifo_v1_01_b;
use rdpfifo_v1_01_b.all;

library opb_ipif_v3_01_b;
use opb_ipif_v3_01_b.all;

library ddr_v1_10_a;
use ddr_v1_10_a.all;

--library cntl_ddr_v1_10_b;
--use cntl_ddr_v1_10_b.all;

entity ddr_cntl2_wrapper is
  port (
    -- Test Bus
    ddr_test_cntl       : in   std_logic_vector(1 downto 0);
    ddr_test_bus        : out  std_logic_vector(19 downto 0);
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_DBus : in std_logic_vector(0 to 31);
    OPB_select : in std_logic;
    OPB_RNW : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_BE : in std_logic_vector(0 to 3);
    Sln_xferAck : out std_logic;
    Sln_errAck : out std_logic;
    Sln_toutSup : out std_logic;
    Sln_retry : out std_logic;
    Sln_DBus : out std_logic_vector(0 to 31);
    DDR_Clk : out std_logic_vector(0 to 0);
    DDR_Clkn : out std_logic_vector(0 to 0);
    DDR_CKE : out std_logic_vector(0 to 0);
    DDR_CSn : out std_logic_vector(0 to 0);
    DDR_RASn : out std_logic;
    DDR_CASn : out std_logic;
    DDR_WEn : out std_logic;
    DDR_DM : out std_logic_vector(0 to 1);
    DDR_BankAddr : out std_logic_vector(0 to 1);
    DDR_Addr : out std_logic_vector(0 to 12);
    DDR_Init_done : out std_logic;
    OPB_Clk : in std_logic;
    OPB_Clk_n : in std_logic;
    Clk90_in : in std_logic;
    Clk90_in_n : in std_logic;
    DDR_Clk90_in : in std_logic;
    DDR_Clk90_in_n : in std_logic;
    OPB_Rst : in std_logic;
    DDR_DQ_I : in std_logic_vector(0 to 15);
    DDR_DQ_O : out std_logic_vector(0 to 15);
    DDR_DQ_T : out std_logic_vector(0 to 15);
    DDR_DQS_I : in std_logic_vector(0 to 1);
    DDR_DQS_O : out std_logic_vector(0 to 1);
    DDR_DQS_T : out std_logic_vector(0 to 1)
  );
end ddr_cntl2_wrapper;

architecture STRUCTURE of ddr_cntl2_wrapper is

  component cntl_ddr2 is
    generic (
      C_INCLUDE_BURST_SUPPORT : INTEGER;
      C_REG_DIMM : INTEGER;
      C_NUM_BANKS_MEM : INTEGER;
      C_NUM_CLK_PAIRS : INTEGER;
      C_FAMILY : STRING;
      C_DDR_TMRD : INTEGER;
      C_DDR_TWR : INTEGER;
      C_DDR_TWTR : INTEGER;
      C_DDR_TRAS : INTEGER;
      C_DDR_TRC : INTEGER;
      C_DDR_TRFC : INTEGER;
      C_DDR_TRCD : INTEGER;
      C_DDR_TRRD : INTEGER;
      C_DDR_TREFC : INTEGER;
      C_DDR_TREFI : INTEGER;
      C_DDR_TRP : INTEGER;
      C_DDR_CAS_LAT : INTEGER;
      C_DDR_DWIDTH : INTEGER;
      C_DDR_AWIDTH : INTEGER;
      C_DDR_COL_AWIDTH : INTEGER;
      C_DDR_BANK_AWIDTH : INTEGER;
      C_MEM0_BASEADDR : std_logic_vector;
      C_MEM0_HIGHADDR : std_logic_vector;
      C_MEM1_BASEADDR : std_logic_vector;
      C_MEM1_HIGHADDR : std_logic_vector;
      C_MEM2_BASEADDR : std_logic_vector;
      C_MEM2_HIGHADDR : std_logic_vector;
      C_MEM3_BASEADDR : std_logic_vector;
      C_MEM3_HIGHADDR : std_logic_vector;
      C_OPB_DWIDTH : INTEGER;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_CLK_PERIOD_PS : INTEGER;
      C_SIM_INIT_TIME_PS : INTEGER
    );
    port (
      -- Test Bus
      ddr_test_cntl       : in   std_logic_vector(1 downto 0);
      ddr_test_bus        : out  std_logic_vector(19 downto 0);
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_select : in std_logic;
      OPB_RNW : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_BE : in std_logic_vector(0 to ((C_OPB_DWIDTH/8)-1));
      Sln_xferAck : out std_logic;
      Sln_errAck : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_retry : out std_logic;
      Sln_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      DDR_Clk : out std_logic_vector(0 to (C_NUM_CLK_PAIRS-1));
      DDR_Clkn : out std_logic_vector(0 to (C_NUM_CLK_PAIRS-1));
      DDR_CKE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
      DDR_CSn : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
      DDR_RASn : out std_logic;
      DDR_CASn : out std_logic;
      DDR_WEn : out std_logic;
      DDR_DM : out std_logic_vector(0 to ((C_DDR_DWIDTH/8)-1));
      DDR_BankAddr : out std_logic_vector(0 to (C_DDR_BANK_AWIDTH-1));
      DDR_Addr : out std_logic_vector(0 to (C_DDR_AWIDTH-1));
      DDR_Init_done : out std_logic;
      OPB_Clk : in std_logic;
      OPB_Clk_n : in std_logic;
      Clk90_in : in std_logic;
      Clk90_in_n : in std_logic;
      DDR_Clk90_in : in std_logic;
      DDR_Clk90_in_n : in std_logic;
      OPB_Rst : in std_logic;
      DDR_DQ_I : in std_logic_vector(0 to (C_DDR_DWIDTH-1));
      DDR_DQ_O : out std_logic_vector(0 to (C_DDR_DWIDTH-1));
      DDR_DQ_T : out std_logic_vector(0 to (C_DDR_DWIDTH-1));
      DDR_DQS_I : in std_logic_vector(0 to ((C_DDR_DWIDTH/8)-1));
      DDR_DQS_O : out std_logic_vector(0 to ((C_DDR_DWIDTH/8)-1));
      DDR_DQS_T : out std_logic_vector(0 to ((C_DDR_DWIDTH/8)-1))
    );
  end component;

begin

  ddr_cntl : cntl_ddr2
    generic map (
      -- C_INCLUDE_BURST_SUPPORT => 0,
      C_INCLUDE_BURST_SUPPORT => 1,
      C_REG_DIMM => 0,
      C_NUM_BANKS_MEM => 1,
      C_NUM_CLK_PAIRS => 1,
      C_FAMILY => "spartan3",
      C_DDR_TMRD => 20000,
      C_DDR_TWR => 20000,
      C_DDR_TWTR => 1,
      C_DDR_TRAS => 60000,
      C_DDR_TRC => 90000,
      C_DDR_TRFC => 100000,
      C_DDR_TRCD => 30000,
      C_DDR_TRRD => 20000,
      C_DDR_TREFC => 70300000,
      C_DDR_TREFI => 7800000,
      C_DDR_TRP => 30000,
      C_DDR_CAS_LAT => 2,
      C_DDR_DWIDTH => 16,
      C_DDR_AWIDTH => 13,
      C_DDR_COL_AWIDTH => 9,
      C_DDR_BANK_AWIDTH => 2,
      C_MEM0_BASEADDR => X"86000000",
      C_MEM0_HIGHADDR => X"87ffffff",
      C_MEM1_BASEADDR => X"ffffffff",
      C_MEM1_HIGHADDR => X"00000000",
      C_MEM2_BASEADDR => X"ffffffff",
      C_MEM2_HIGHADDR => X"00000000",
      C_MEM3_BASEADDR => X"ffffffff",
      C_MEM3_HIGHADDR => X"00000000",
      C_OPB_DWIDTH => 32,
      C_OPB_AWIDTH => 32,
      C_OPB_CLK_PERIOD_PS => 13333,
      C_SIM_INIT_TIME_PS => 200000000
    )
    port map (
      ddr_test_cntl  => ddr_test_cntl,
      ddr_test_bus   => ddr_test_bus,
      OPB_ABus => OPB_ABus,
      OPB_DBus => OPB_DBus,
      OPB_select => OPB_select,
      OPB_RNW => OPB_RNW,
      OPB_seqAddr => OPB_seqAddr,
      OPB_BE => OPB_BE,
      Sln_xferAck => Sln_xferAck,
      Sln_errAck => Sln_errAck,
      Sln_toutSup => Sln_toutSup,
      Sln_retry => Sln_retry,
      Sln_DBus => Sln_DBus,
      DDR_Clk => DDR_Clk,
      DDR_Clkn => DDR_Clkn,
      DDR_CKE => DDR_CKE,
      DDR_CSn => DDR_CSn,
      DDR_RASn => DDR_RASn,
      DDR_CASn => DDR_CASn,
      DDR_WEn => DDR_WEn,
      DDR_DM => DDR_DM,
      DDR_BankAddr => DDR_BankAddr,
      DDR_Addr => DDR_Addr,
      DDR_Init_done => DDR_Init_done,
      OPB_Clk => OPB_Clk,
      OPB_Clk_n => OPB_Clk_n,
      Clk90_in => Clk90_in,
      Clk90_in_n => Clk90_in_n,
      DDR_Clk90_in => DDR_Clk90_in,
      DDR_Clk90_in_n => DDR_Clk90_in_n,
      OPB_Rst => OPB_Rst,
      DDR_DQ_I => DDR_DQ_I,
      DDR_DQ_O => DDR_DQ_O,
      DDR_DQ_T => DDR_DQ_T,
      DDR_DQS_I => DDR_DQS_I,
      DDR_DQS_O => DDR_DQS_O,
      DDR_DQS_T => DDR_DQS_T
    );

end architecture STRUCTURE;