📄 cntl_ddr2.vhd
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-- No ECC supported in OPB DDR controller (constants used to turn off ECC)
constant NO_ECC_SUPPORT : integer := 0;
constant NUM_ECC_BITS : integer := 1; -- set equal to 1 so ECC vector size = 0
constant NO_ECC_CHK_BITS_WR : std_logic_vector (0 to NUM_ECC_BITS*2-1) := (others => '0');
constant NO_DDR_DQ_ECC_I : std_logic_vector (0 to NUM_ECC_BITS-1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Used Signals
signal ip2bus_rdack : std_logic;
signal ip2bus_wrack : std_logic;
signal ip2bus_ack : std_logic;
signal ip2bus_addrack : std_logic;
signal ip2bus_wraddrack : std_logic;
signal ip2bus_rdaddrack : std_logic;
signal ip2bus_toutsup : std_logic;
signal ip2bus_retry : std_logic;
signal ip2bus_errack : std_logic;
signal ip2bus_postedwrinh : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal ip2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1);
signal ip2bus_intrevent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1);
signal bus2ip_addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal bus2ip_addrvalid : std_logic;
signal bus2ip_data : std_logic_vector(0 to C_OPB_DWIDTH - 1);
signal bus2ip_rnw : std_logic;
signal bus2ip_rdreq : std_logic;
signal bus2ip_wrreq : std_logic;
signal bus2ip_cs : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal bus2ip_ce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_be : std_logic_vector(0 to (C_OPB_DWIDTH / 8) - 1);
signal bus2ip_burst : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-------------------------------------------------------------------------------
-- Component Instantiations
-------------------------------------------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_b.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => C_INCLUDE_BURST_SUPPORT,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Bus2IP_CS => bus2ip_cs,
--Bus2IP_CE => bus2ip_ce,
Bus2IP_CE => open,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => bus2ip_data,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_AddrValid => bus2ip_addrvalid,
Bus2IP_BE => bus2ip_be,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_Burst => bus2ip_burst,
IP2Bus_Data => ip2bus_data,
IP2Bus_Ack => ip2bus_ack,
IP2Bus_AddrAck => ip2bus_addrack,
IP2Bus_Error => ip2bus_errack,
IP2Bus_Retry => ip2bus_retry,
IP2Bus_ToutSup => ip2bus_toutsup,
IP2Bus_PostedWrInh => ip2bus_postedwrinh,
IP2RFIFO_Data => ZERO_DATA,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_INTR,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => Bus2IP_Reset
);
-------------------------------------------------------------------------------
-- Miscellaneous assignments to match DDR controller to IPIC
-------------------------------------------------------------------------------
bus2ip_rdreq <= or_reduce(bus2ip_rdce(0 to C_NUM_BANKS_MEM-1)) and bus2ip_addrvalid;
bus2ip_wrreq <= or_reduce(bus2ip_wrce(0 to C_NUM_BANKS_MEM-1)) and bus2ip_addrvalid;
ip2bus_ack <= (ip2bus_wrack or ip2bus_rdack) when
or_reduce(Bus2IP_CS(0 to C_NUM_BANKS_MEM-1)) = '1' else '0';
ip2bus_addrack <= (ip2bus_wraddrack or ip2bus_rdaddrack) when
or_reduce(Bus2IP_CS(0 to C_NUM_BANKS_MEM-1)) = '1' else '0';
ip2bus_postedwrinh <= (others => '0') when (C_INCLUDE_BURST_SUPPORT = 1) else (others => '1');
-----------------------------------------------------------------------------
-- Instantiate the DDR Controller
-----------------------------------------------------------------------------
--DDR_CTRL_I: entity ddr_v1_10_a.ddr_controller
DDR_CTRL_I: ddr_controller2
generic map (
C_REG_DIMM => C_REG_DIMM ,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM ,
C_NUM_CLK_PAIRS => C_NUM_CLK_PAIRS ,
C_FAMILY => C_FAMILY ,
C_DDR_TMRD => C_DDR_TMRD ,
C_DDR_TWR => C_DDR_TWR ,
C_DDR_TWTR => C_DDR_TWTR ,
C_DDR_TRAS => C_DDR_TRAS ,
C_DDR_TRC => C_DDR_TRC ,
C_DDR_TRFC => C_DDR_TRFC ,
C_DDR_TRCD => C_DDR_TRCD ,
C_DDR_TRRD => C_DDR_TRRD ,
C_DDR_TREFC => C_DDR_TREFC ,
C_DDR_TREFI => C_DDR_TREFI ,
C_DDR_TRP => C_DDR_TRP ,
C_DDR_CAS_LAT => C_DDR_CAS_LAT ,
C_DDR_DWIDTH => C_DDR_DWIDTH ,
C_DDR_AWIDTH => C_DDR_AWIDTH ,
C_DDR_COL_AWIDTH => C_DDR_COL_AWIDTH ,
C_DDR_BANK_AWIDTH => C_DDR_BANK_AWIDTH ,
C_DDR_BRST_SIZE => DDR_BRST_SIZE ,
C_IPIF_DWIDTH => C_OPB_DWIDTH ,
C_IPIF_AWIDTH => C_OPB_AWIDTH ,
C_INCLUDE_BURSTS => C_INCLUDE_BURST_SUPPORT ,
C_CLK_PERIOD => C_OPB_CLK_PERIOD_PS ,
C_OPB_BUS => OPB_BUS ,
C_PLB_BUS => PLB_BUS ,
C_SIM_INIT_TIME_PS => C_SIM_INIT_TIME_PS , -- simulation only generic (set to 200us)
C_INCLUDE_ECC_SUPPORT => NO_ECC_SUPPORT ,
NUM_ECC_BITS => NUM_ECC_BITS
)
port map (
ddr_test_cntl => ddr_test_cntl,
ddr_test_bus => ddr_test_bus,
Bus2IP_Addr => bus2ip_addr ,
Bus2IP_BE => bus2ip_be ,
Bus2IP_Data => bus2ip_data ,
Bus2IP_RNW => bus2ip_rnw ,
Bus2IP_RdReq => bus2ip_rdreq ,
Bus2IP_WrReq => bus2ip_wrreq ,
Bus2IP_Burst => '0' ,
Bus2IP_IBurst => bus2ip_burst , -- all OPB bursts are indeterminate
Bus2IP_CS => bus2ip_cs ,
IP2Bus_Data => ip2bus_data ,
IP2Bus_WrAddrAck => ip2bus_wraddrack ,
IP2Bus_RdAddrAck => ip2bus_rdaddrack ,
IP2Bus_RdAck => ip2bus_rdack ,
IP2Bus_WrAck => ip2bus_wrack ,
IP2Bus_ErrAck => ip2bus_errack ,
IP2Bus_Retry => ip2bus_retry ,
IP2Bus_ToutSup => ip2bus_toutsup ,
ECC_chk_bits_wr => NO_ECC_CHK_BITS_WR , -- ECC not supported
ECC_chk_bits_rd => open , -- ECC not supported
DDR_Clk => DDR_Clk ,
DDR_Clkn => DDR_Clkn ,
DDR_CKE => DDR_CKE ,
DDR_CSn => DDR_CSn ,
DDR_RASn => DDR_RASn ,
DDR_CASn => DDR_CASn ,
DDR_WEn => DDR_WEn ,
DDR_DM => DDR_DM ,
DDR_BankAddr => DDR_BankAddr ,
DDR_Addr => DDR_Addr ,
DDR_DQ_o => DDR_DQ_o ,
DDR_DQ_i => DDR_DQ_i ,
DDR_DQ_t => DDR_DQ_t ,
DDR_DQS_i => DDR_DQS_i ,
DDR_DQS_o => DDR_DQS_o ,
DDR_DQS_t => DDR_DQS_t ,
DDR_DM_ECC => open , -- ECC not supported
DDR_DQ_ECC_o => open , -- ECC not supported
DDR_DQ_ECC_i => NO_DDR_DQ_ECC_I , -- ECC not supported
DDR_DQ_ECC_t => open , -- ECC not supported
DDR_DQS_ECC_i => '0' , -- ECC not supported
DDR_DQS_ECC_o => open , -- ECC not supported
DDR_DQS_ECC_t => open , -- ECC not supported
DDR_Init_done => DDR_Init_done ,
Sys_Clk => OPB_Clk ,
Sys_Clk_n => OPB_Clk_n ,
Clk90_in => Clk90_in ,
Clk90_in_n => Clk90_in_n ,
DDR_Clk90_in => DDR_Clk90_in ,
DDR_Clk90_in_n => DDR_Clk90_in_n ,
Rst => OPB_Rst
);
end implementation;
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